Holtek BS83B24C Manual page 80

• CTMC0 Register
Bit 7
Name CTPAU
R/W R/W
POR 0
Bit 7 CTPAU: CTM Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the CTM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
CTCK2~CTCK0: Select CTM Counter clock
Bit 6~4
000: f
001: f
010: f
011: f
100: f
101: f
110: CTCK rising edge clock
111: CTCK falling edge clock
These three bits are used to select the clock source for the CTM. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
f
SYS
can be found in the oscillator section.
Bit 3 CTON: CTM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the CTM. Setting the bit high enables
the counter to run, clearing the bit to 0 disables the CTM. Clearing this bit to zero
will stop the counter from counting and turn off the CTM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again.
If the CTM is in the Compare Match Output Mode or the PWM Output Mode then
the CTM output pin will be reset to its initial condition, as specified by the CTOC bit,
when the CTON bit changes from low to high.
Bit 2~0 CTRP2~CTRP0: CTM CCRP 3-bit register, compared with the CTM Counter bit 9~bit 7
Comparator P Match Period
000: 1024 CTM clocks
001: 128 CTM clocks
010: 256 CTM clocks
011: 384 CTM clocks
100: 512 CTM clocks
101: 640 CTM clocks
110: 768 CTM clocks
111: 896 CTM clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter's highest three bits. The result of this
comparison can be selected to clear the internal counter if the CTCCLR bit is set to
zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.00
6 5
CTCK� CTCK1 CTCK0
R/W R/W
0 0
/4
SYS
SYS
/16
H
/64
H
SUB
SUB
is the system clock, while f and f
H
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BS83B24C/BS83C40C
Touch Flash MCU
4 3 2
CTON CTRP�
R/W R/W R/W
0 0 0
are other internal clocks, the details of which
SUB
1 0
CTRP1 CTRP0
R/W R/W
0 0
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