Holtek BS83B24C Manual page 106

SIMEN: USIM SPI/I
Bit 1
0: Disable
1: Enable
The bit is the overall on/off control for the USIM SPI/I
bit is cleared to zero to disable the USIM SPI/I
SCS, or SDA and SCL lines will lose their SPI or I
current will be reduced to a minimum value. When the bit is high the USIM SPI/I
interface is enabled. If the USIM is configured to operate as an SPI interface via the
UMD and SIM2~SIM0 bits, the contents of the SPI control registers will remain at the
previous settings when the SIMEN bit changes from low to high and should therefore
be first initialised by the application program. If the USIM is configured to operate as
an I
low to high, the contents of the I
at the previous settings and should therefore be first initialised by the application
program while the relevant I
be set to their default states.
Bit 0 SIMICF: USIM SPI Incomplete Flag
0: USIM SPI incomplete condition is not occurred
1: USIM SPI incomplete condition is occurred
This bit is only available when the USIM is configured to operate in an SPI slave
mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both
being set to 1 but the SCS line is pulled high by the external master device before the
SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with
the TRF bit. When this condition occurs, the corresponding interrupt will occur if the
interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF
bit is set to 1 by software application program.
• SIMC2 Register
Bit 7
Name D�
R/W
R/W
POR
0
Bit 7~6 D7~D6: Undefined bits
These bits can be read or written by the application program.
Bit 5 CKPOLB: SPI clock line base condition selection
0: The SCK line will be high when the clock is inactive
1: The SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4 CKEG: SPI SCK clock active edge type selection
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Rev. 1.00
C Enable Control
2
C interface via the UMD and SIM2~SIM0 bits and the SIMEN bit changes from
2
C control bits such as HTX and TXAK will remain
2
C flags such as HCF, HAAS, HBB, SRW and RXAK will
2
6 5
D6 CKPOLB CKEG
R/W R/W R/W
0 0
106
BS83B24C/BS83C40C
Touch Flash MCU
C interface. When the SIMEN
2
C interface, the SDI, SDO, SCK and
2
C function and the USIM operating
2
4 3 2
MLS CSEN
R/W R/W
0 0 0
C
2
0
1
WCOL TR�
R/W R/W
0
0
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