Holtek BS83B24C Manual page 117

BS83B24C/BS83C40C
Touch Flash MCU
I C Bus Start Signal
2
The START signal can only be generated by the master device connected to the I
slave device. This START signal will be detected by all devices connected to the I
this indicates that the I
when a high to low transition on the SDA line takes place when the SCL line remains high.
I C Slave Address
2
The transmission of a START signal by the master will be detected by all devices on the I
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal USIM
I C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit,
2
defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave
device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device
will also set the status flag HAAS when the addresses match.
As an USIM I C bus interrupt can come from three sources, when the program enters the interrupt
2
subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source
has come from a matching slave address or from the completion of a data byte transfer or from the
I C bus time-out occurrence. When a slave address is matched, the device must be placed in either
2
the transmit mode and then write data to the SIMD register, or in the receive mode where it must
implement a dummy read from the SIMD register to release the SCL line.
I C Bus Read/Write Signal
2
The SRW bit in the SIMC1 register defines whether the master device wishes to read data from the
I C bus or write data to the I
2
be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes
to read data from the I
a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I
bus, therefore the slave device must be setup to read data from the I
Rev. 1.00
Sta�t
CLR UMD
SET SIM[�:0]=110
SET SIMEN
W�ite Slave
Add�ess to SIMA
No
�
I C B�s
Inte���pt=?
CLR USIME
Poll USIM� to decide
�
when to go to I C B�s ISR
Go to Main P�og�am
I C Bus Initialisation Flow Chart
2
C bus is busy and therefore the HBB bit will be set. A START condition occurs
2
C bus. The slave device should examine this bit to determine if it is to
2
C bus, therefore the slave device must be setup to send data to the I
2
11�
Yes
SET USIME
Wait fo� Inte���pt
Go to Main P�og�am
C bus and not by the
2
C bus. When detected,
2
C bus as
2
C bus as a receiver.
2
�e���a�� 0�� �01�
C bus.
2
C
2