Holtek BS83B24C Manual page 75

BS83B24C/BS83C40C
Touch Flash MCU
I/O Pin Structures
The accompanying diagram illustrates the internal structures of the I/O logic function. As the exact
logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to
assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
W�ite Cont�ol Registe�
Read Cont�ol Registe�
W�ite Data Registe�
Read Data Registe�
Programming Considerations
Within the user program, one of the things first to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set to high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or
by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i"
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Rev. 1.00
Cont�ol Bit
Data B�s D Q
CK Q
S
Chip Reset
Data Bit
D Q
CK Q
S
M
S�stem Wake-�p
Logic Function Input/Output Structure
�5
VDD
P�ll-high
Registe� Weak
Select
P�ll-�p
U
X
PA onl�
wake-�p Select
I/O pin
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