Holtek BS83B24C Manual page 123

BS83B24C/BS83C40C
Touch Flash MCU
• SIMC0 Register
Bit 7
Name SIM�
R/W R/W
POR 1
Bit 7~5 SIM2~SIM0: USIM SPI/I
When the UMD bit is cleared to zero, these bits setup the SPI or I
of the USIM function. Refer to the SPI or I
Bit 4 UMD: UART mode selection bit
0: SPI or I
1: UART mode
This bit is used to select the UART mode. When this bit is cleared to zero, the actual
SPI or I
must be set low for SPI or I
Bit 3~2 SIMDEB1~SIMDEB0: I
Refer to the I
Bit 1 SIMEN: USIM SPI/I
This bit is only available when the USIM is configured to operate in an SPI or I
mode with the UMD bit set low. Refer to the SPI or I
details.
SIMICF: USIM SPI Incomplete Flag
Bit 0
Refer to the SPI register section.
• UUSR Register
The UUSR register is the status register for the UART, which can be read by the program to
determine the present status of the UART. All flags within the UUSR register are read only. Further
explanation on each of the flags is given below:
Bit 7
Name UPERR
R/W R
POR 0
UPERR: Parity error flag
Bit 7
0: No parity error is detected
1: Parity error is detected
The UPERR flag is the parity error flag. When this read only flag is "0", it indicates a
parity error has not been detected. When the flag is "1", it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd
or even) is selected. The flag can also be cleared to 0 by a software sequence which
involves a read to the status register UUSR followed by an access to the UTXR_RXR
data register.
UNF: Noise flag
Bit 6
0: No noise is detected
1: Noise is detected
The UNF flag is the noise flag. When this read only flag is "0", it indicates no noise
condition. When the flag is "1", it indicates that the UART has detected noise on the
receiver input. The UNF flag is set during the same cycle as the URXIF flag but will
not be set in the case of as overrun. The UNF flag can be cleared to 0 by a software
sequence which will involve a read to the status register UUSR followed by an access
to the UTXR_RXR data register.
Rev. 1.00
6 5 4
SIM1 SIM0 UMD
R/W R/W R/W
1 1 0
C Operating Mode Control
2
C mode
2
C mode can be selected using the SIM2~SIM0 bits. Note that the UMD bit
2
C mode.
2
C Debounce Time Selection
2
C register section.
2
C Enable Control
2
6 5 4
UN� U�ERR UOERR
R R R
0 0 0
1�3
3 2 1
SIMDEB1 SIMDEB0 SIMEN
R/W R/W R/W
0 0 0
C operating mode
2
C register section for more details.
2
C register section for more
2
3 2 1
URIDLE URXI� UTIDLE
R R R
1 0 1
�e���a�� 0�� �01�
0
SIMIC�
R/W
0
C
2
0
UTXI�
R
1