Holtek BS83B24C Manual page 93

BS83B24C/BS83C40C
Touch Flash MCU
PTOC: PTM PTP Output control
Bit 3
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTM output pin. Its operation depends upon
whether PTM is being used in the Compare Match Output Mode or in the PWM
Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/
Counter Mode. In the Compare Match Output Mode it determines the logic level of
the PTM output pin before a compare match occurs. In the PWM Output Mode/Single
Pulse Output Mode it determines if the PWM signal is active high or active low.
Bit 2 PTPOL: PTM PTP Output polarity control
0: Non-invert
1: Invert
This bit controls the polarity of the PTP output pin. When the bit is set high the PTM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
PTM is in the Timer/Counter Mode.
PTCAPTS: PTM Capture Trigger Source selection
Bit 1
0: From PTPI pin
1: From PTCK pin
PTCCLR: PTM Counter Clear condition selection
Bit 0
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
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