Holtek BS83B24C Manual page 107

BS83B24C/BS83C40C
Touch Flash MCU
MLS: SPI data shift order
Bit 3
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin control
Bit 2
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS
pin will be enabled and used as a select pin.
Bit 1 WCOL: SPI write collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SIMD register during a data
transfer operation. This writing operation will be ignored if data is being transferred.
The bit can be cleared to 0 by the application program.
Bit 0 TRF: SPI Transmit/Receive complete flag
0: SPI data is being transferred
1: SPI data transmission is completed
The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when
an SPI data transmission is completed, but must set to "0" by the application program.
It can be used to generate an interrupt.
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is completed, the TRF flag will be set high automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output an SCS signal to enable the slave devices before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCK signal depending upon the configurations of the CKPOLB bit and
CKEG bit. The accompanying timing diagram shows the relationship between the slave data and
SCK signal for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function in certain IDLE Modes if the clock source used by the SPI
interface is still active.
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