Holtek BS83B24C Manual page 86

Timer/Counter Mode
To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the CTM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively.
The PWM function within the CTM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but of
varying duty cycle on the CTM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM Output Mode, the CTCCLR bit has no effect on the
PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform,
one register is used to clear the internal counter and thus control the PWM waveform frequency,
while the other one is used to control the duty cycle. Which register is used to control either
frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM
waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and
CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The CTOC bit In the CTMC1 register is used to
select the required polarity of the PWM waveform while the two CTIO1 and CTIO0 bits are used to
enable the PWM output or to force the CTM output pin to a fixed high or low level. The CTPOL bit
is used to reverse the polarity of the PWM output waveform.
• 10-bit CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=0
If f =8MHz, CTM clock source is f
SYS
The CTM PWM output frequency=(f
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=1
The PWM output period is determined by the CCRA register value together with the CTM clock
while the PWM duty cycle is defined by the CCRP register value.
Rev. 1.00
CCRP 1~7
Pe�iod CCRP × 1��
D�t� CCRA
/4, CCRP=2, CCRA=128,
SYS
/4)/(2×128)=f /1024=7.812kHz, duty=128/(2×128)=50%.
SYS SYS
CCRP 1~7
Pe�iod CCRA
D�t� CCRP × 1��
�6
BS83B24C/BS83C40C
Touch Flash MCU
0
10�4
0
10�4
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