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CPU
CPU Read/Write Cycle
The H8/300L CPU operates on either the system clock ø or the subclock ø
generated by the clock generator circuits. A single period of either the ø or ø
called a state. Accesses, which differ for the on-chip memory and the on-chip peripheral
modules, take place in basic bus cycles, which take either 2 or 3 states.
On-Chip Memory Access Timing (RAM and ROM): On-chip memory is accessed in two
states. The data bus can be used in either 8-bit or 16-bit widths for byte or word accesses.
On-Chip Peripheral Module Access Timing: On-chip peripheral modules are accessed in
two or three states. The data bus width in this case is 8 bits, so only byte access is possible.
State T
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus
(read)
Internal write signal
Internal data bus
(write)
Two-State Access
State T
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus
(read)
Internal write signal
Internal data bus
(write)
Bus cycle
State T
1
2
Address
Read data
Write data
Bus cycle
State T
1
2
Address
Read data
Write data
State T
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus
(read)
Internal write signal
Internal data bus
(write)
Three-State Access
44
, which are
SUB
clock is
SUB
Bus cycle
State T
State T
1
2
Address
Read data
Write data
3
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