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CPU
No.
Addressing Mode, Instruction Format
Register indirect
with pre-decrement
@–Rn
15
OP
4
Register indirect
with post-decrement
@Rn+
15
OP
Immediate #xx:8
15
OP
5
Immediate #xx:16
15
Absolute address @aa:8
15
OP
6
Absolute address @aa:16
15
PC-relative @(d:8,PC)
7
15
OP
Memory indirect @@aa:8
15
OP
8
<Notation>
General register
reg:
#IMM:
Immediate data
d:
Displacement
15
7 6
4
0
reg
15
7 6
4
0
reg
One is added when the
operand size is byte,
and 2 is added when
the operand size is word.
8
7
0
#IMM
0
OP
#IMM
8
7
0
aa:8
0
OP
aa:16
15
8
7
0
d:8
8
7
0
aa:8
15
15
aa:
Absolute address
OP:
Op-code
PC:
Program counter
Effective Address Calculation
Register contents (16 bits)
1 or 2
Register contents (16 bits)
1 or 2
PC contents
Sign extension
d:8
8
7
aa:8
H'00
Memory contents (16 bits)
34
EA
0
15
0
15
The operand is the single
byte of immediate data.
The operand is the two
bytes of immediate data.
15
8
H'FF
15
0
15
0
0
15
0
0
7
0
0
0
0
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