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APPENDIX B
FIRMWARE
B.l
INTRODUCTION
This appendix describes the user commands for the communication
firmware supplied with the iSBC 546, iSBC 547 and iSBC 548 boards.
The firmware makes the boards into terminal controllers. The
primary features of the firmware are listed and briefly summarized
in Table B-l.
B.2
FIRMWARE OVERVIEW
NOTE
Throughout this appendix the word
controllers indicates all three boards,
iSBC 546, iSBC 547 and iSBC 548.
References to individual boards will
include the model number.
The iSBC 546/547/548 firmware is released as a set of two Intel
EPROMs. The firmware makes the three boards into intelligent
terminal controllers which can provide a MULTIBUS host CPU with
either four (iSBC 546) or eight (iSBC 547 and iSBC 548)
asynchronous serial channels.
MULTIBUS host CPUs view the iSBC 546/547/548 boards as slave
peripheral controllers. The host and the controllers communicate
via shared data structures and a message passing scheme implemented
in the controllers on-board dual ported RAM. The host CPU signals
the controller with the hardware I/O mapped flag byte mechanism on
the controllers. The controllers signal the host CPU by requesting
an interrupt on a jumper selectable MULTIBUS interrupt line.
B-1
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