Multibus Interrupt Jumpers; Memory Mapping Jumpers - Intel iSBC 546 Hardware Reference Manual

High performance terminal controllers
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JUMPER INFORMATION
A.3
MULTIBUS
INTERRUPT JUMPERS
The selection of which MULTI BUS Interrupt is used to interrupt the
host is jumper selectable. A list of interrupts and there
associated jumpers (the jumper installed selects its interrupt) is
shown below:
Interru:et
Jum:eer
INTO*
E20 - E21 Selectable on iSBC 547/548 only
INTl*
E19 - E24 Selectable on all boards
INT2*
E25 - E24 Default installation iSBC 546
Selectable on all boards
INT3*
E27 - E24 Default installation iSBC 547
and iSBC 548
Selectable on all boards
INT4*
E23 - E24 Selectable on all boards
INT5*
E18 - E21 Selectable on iSBC 547/548 only
INT6*
E22 - E21 Selectable on iSBC 547/548 only
INT7*
E26 - E21 Selectable on iSBC 547/548 only
A.4
MEMORY MAPPING JUMPERS
Memory mapping of the DRAM is a jumper configurable option on all
three controller boards. The jumper combinations and the addresses
they select are shown in Table A-4. The jumpers and addresses are
identical on all boards.
A-5

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