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No. 2D730-148E*O
(3)
Explanation of the block diagram
The figure on the next page shows the top-level functional block diagram of the VI board.
There are two separate PCI master/target
devices on the VI board.
One is the VPDM
(video processor display manager) ASIC and the other is the VPIF (video processor image
formatter) decoder FPGA. Each PCI master/target
interface in the devices supports 64-bit
address/data
transactions
at a 33-MHz bus speed. The PCI bus allows the VPDM to
receive image data (e.g. 2D images, Doppler traces, ECG waveforms,
etc.) from the BE
board. It also allows both the VPDM ASIC and the decoder FPGA to communicate
with
each other.
The digital SVGA link from the graphics subsystem of the RM to the VI carries 24-bit RGB
data for the CPU overlay graphics and horizontal and vertical synchronization
signals. The
RM also sends the pixel clock signal to the VI, which is synchronized
with the RGB data.
The VPDM drives the system monitor through a triple 8-bit video DAC to display
ultrasound images with superimposed
overlay graphics.
The maximum resolution
supported will be 800x600 at a non-interlaced
vertical refresh rate of 60 Hz for NTSC
systems and 75 Hz for PAL systems.
The 16-bit data bus from the VPDM to the VPIF encoder FPGA carries 16-bit YCbCr (4:2:2)
non-interlaced
video data with a resolution of 800x600 pixels. The VPDM sends video
data that contains the video information
displayed on the system monitor to the VPIF,
where the data is converted to the NTSC/PAL image size and format and is then routed to
the IO board.
The NTSC/PAL video encoder receives image data in the 4:2:2 YCbCr format from the
VPIF encoder FPGA and converts it to analog signals for an external monitor or a VCR
The output analog signals are Y and C, color composite and RGB components.
The NTSC/PAL video decoder converts analog Y/C signals from an external video device
to image data in the 4:2:2 YCbCr format.
Hsync, Vsync, field ID, and blanking information
are included in the data stream.
In VCR playback mode, the decoded VCR video data is
scaled up and converted to non-interlaced
video data in the VPIF decoder FPGA and is
then sent to the VPDM via the PCI bus.
The system audio control block provides input/output
audio source select, volume and
tone control, test tone generation,
crossover networks, and audio D/A conversion.
(4)
Equivalent units in the PV series
The functions of this PWB are equivalent to those performed
by the RGB-CONV and TV-
PROC in the PV series.
4-36
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