Toshiba Aplio SSA-770A Service Manual page 137

INPUTS
FROM
TR BOARDS
I I
CHO
DR ASICS
(4)
I
1
PHYSIO INPUT
INPUT FROM CB BOARD
LOCAL/MICROPROCESSOR BUS
I I
-
' PCI INTER
PCI
BUS
b FACE
FE BUS
- ID
PROM
BOOT
PROM
FP ASIC FP FPGA
I
I I
I
+
b
SIP FPGA
DSP
DSP
b
IP
LOCAL
ROUTER
6701
SDRAM
OUTPUT TO PHYSIO
I I
TRIGGER CONTROL
I
FE TEST BUS
TAG TES
'p~co~!fiol 1 BE TEST BUS RCBECK
I
PECL CLOCK
Block diagram of the BE board
IP INTERFACE
Ei 40-MHz TTL CLOCKS
TO