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DECA User Manual
www.terasic.com
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May 22, 2015

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  • Page 1 DECA User Manual www.terasic.com May 22, 2015...

  • Page 2: Table Of Contents

    2.2 Block Diagram of the DECA Board ................... 7 Chapter 3 Using the DECA Board ............... 10 3.1 Configuration of MAX 10 FPGA on DECA ................10 3.2 Board Status Elements......................16 3.3 Clock Circuitry ......................... 17 3.4 Peripherals Connected to the FPGA ..................18 Chapter 4 DECA System Builder ..............
  • Page 3 8.1 Internal Configuration ......................120 8.2 Factory Default Dual Boot Image ..................122 8.3 Using Dual Compressed Images .................... 122 Chapter 9 Appendix ................... 133 9.1 Revision History ........................133 9.2 Copyright Statement ....................... 133 DECA User Manual www.terasic.com May 22, 2015...

  • Page 4: Deca Development Kit

    DDR3 memory, video and audio capabilities, Ethernet networking, and much more that promise many exciting applications. The DECA Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later.

  • Page 5: Deca System Cd

     AR0833 8.0M Camera Module  5V DC power adapter The DECA System CD contains all the documents and supporting materials associated with DECA, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://cd-deca.terasic.com.

  • Page 6: Introduction Of The Deca Board

    Introduction of the DECA Board Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the location of the connectors and key components. Figure 2-1 DECA development board (top view) DECA User Manual www.terasic.com May 22, 2015...
  • Page 7 Figure 2-2 DECA development board (bottom view) The DECA board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the board:  Altera MAX® 10 10M50DAF484C6G device ...

  • Page 8: Block Diagram Of The Deca Board

    All the connections are established through the MAX 10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to implement any system design. Figure 2-3 Block diagram of DECA DECA User Manual www.terasic.com...
  • Page 9  Two MAX 10 FPGA ADC SMA inputs  HDMI TX, incorporates HDM v1.4 features, including 3D video supporting  24-bit CD-quality audio CODEC with line-in, line-out jacks  MIPI connector interface supports camera module application DECA User Manual www.terasic.com May 22, 2015...
  • Page 10  2 push-buttons  2 slide switches  8 blue user LEDs  One proximity/ambient lighter sensor  One humidity and temperature sensor  One temperature sensor  One accelerometer  5V DC input DECA User Manual www.terasic.com May 22, 2015...

  • Page 11: Using The Deca Board

    (CFM) which provides non-volatile storage for the bit stream. The information is retained within CFM even if the DECA board is turned off. When the board is powered on, the configuration data in the CFM is automatically loaded into the MAX 10 FPGA.
  • Page 12 The following shows how the FPGA is programmed in JTAG mode step by step. 1. Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-2 Figure 3-2 Detect FPGA device in JTAG mode DECA User Manual www.terasic.com May 22, 2015...
  • Page 13 3. FPGA is detected, as shown in Figure 3-4. Figure 3-4 FPGA detected in Quartus programmer 4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in DECA User Manual www.terasic.com May 22, 2015...
  • Page 14 Figure 3-5. Figure 3-5 Open the .sof file to be programmed into the FPGA device 5. Select the .sof file to be programmed, as shown in Figure 3-6. DECA User Manual www.terasic.com May 22, 2015...
  • Page 15 Figure 3-6 Select the .sof file to be programmed into the FPGA device 6. Click “Program/Configure” check box and then click “Start” button to download the .sof file into the FPGA device, as shown in Figure 3-7. DECA User Manual www.terasic.com May 22, 2015...
  • Page 16 This configuration data is automatically loaded from the CFM into the MAX 10 devices when the board is powered up.  Please refer to Chapter 8: Programming the Configuration Flash Memory (CFM) for the basic programming instruction on the configuration flash memory (CFM). DECA User Manual www.terasic.com May 22, 2015...

  • Page 17: Board Status Elements

    In addition to the 8 LEDs that FPGA device can control, there are 4 indicators which can indicate the board status (See Figure 3-9), please refer the details in Table 3-1 Figure 3-9 LED Indicators on DECA Table 3-1 LED Indicators Board Reference LED Name Description 3.3V Power...

  • Page 18: Clock Circuitry

    MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3-2. DECA User Manual www.terasic.com May 22, 2015...

  • Page 19: Peripherals Connected To The Fpga

    Figure 3-10 Block diagram of the clock distribution on DECA Table 3-2 Pin Assignment of Clock Inputs Signal Name FPGA Pin No. Description I/O Standard MAX10_CLK1_50 PIN_M8 50 MHz clock input 2.5V MAX10_CLK2_50 PIN_P11 50 MHz clock input 3.3V DDR3_CLK_50...
  • Page 20 Figure 3-11 Connections between the push-buttons and the MAX 10 FPGA Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced Figure 3-12 Switch debouncing There are two CapSense buttons connected to the FPGA, as shown in Figure 3-13. Through the DECA User Manual www.terasic.com May 22, 2015...
  • Page 21 FPGA. When the switch is set to the DOWN position (towards the edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is generated to the FPGA. DECA User Manual www.terasic.com May 22, 2015...
  • Page 22 MAX 10 FPGA. Table 3-3, Table 3-4, Table 3-5 Table 3-6 list the pin assignment of user push-buttons, CapSense-buttons, switches, and LEDs. Figure 3-15 Connections between the LEDs and the Cyclone V SoC FPGA DECA User Manual www.terasic.com May 22, 2015...
  • Page 23 PIN_C5 LED [7] 1.2V 3.4.2 The DECA has implemented a power monitor chip to monitor the FPGA core power voltage and current. Figure 3-16 shows the connection between the power monitor chip and the MAX 10 FPGA. The power monitor chip monitors both shunt voltage drops and FPGA core power voltage.
  • Page 24 The maximum power consumption allowed for a daughter card connected to one or two GPIO ports is shown in Table 3-8. Table 3-8 Voltage and Max. Current Limit of Expansion Header(s) Supplied Voltage Max. Current Limit 3.3V DECA User Manual www.terasic.com May 22, 2015...
  • Page 25 GPIO (P8) Connection 0[14] 3.3V GPIO0_D[15] PIN_AA16 GPIO (P8) Connection 0[15] 3.3V GPIO0_D[16] PIN_AB16 GPIO (P8) Connection 0[16] 3.3V GPIO0_D[17] PIN_W16 GPIO (P8) Connection 0[17] 3.3V GPIO0_D[18] PIN_AB15 GPIO (P8) Connection 0[18] 3.3V DECA User Manual www.terasic.com May 22, 2015...
  • Page 26 GPIO (P9) Connection 1[15] 3.3V GPIO1_D[16] PIN_W9 GPIO (P9) Connection 1[16] 3.3V GPIO1_D[17] PIN_W5 GPIO (P9) Connection 1[17] 3.3V GPIO1_D[18] PIN_R9 GPIO (P9) Connection 1[18] 3.3V GPIO1_D[19] PIN_W4 GPIO (P9) Connection 1[19] 3.3V DECA User Manual www.terasic.com May 22, 2015...
  • Page 27 The DECA offers high-quality 24-bit audio via the Texas Instruments TLV320AIC3254 audio CODEC (Encoder/Decoder). This chip on DECA supports, line-in, and line-out ports. One of line-in inputs is both connected to the FPGA ADC and the audio CODEC ADC, it allows user to implement audio applications via the MAX 10 build-in ADC.
  • Page 28 1.5V 3.4.5 The DECA board implements two analog input SMA connectors. The analog inputs are amplified and translated by Texas Instruments INA159 gain of 0.2 level translation difference amplifier, then the amplifier’s outputs are fed to dedicated single-ended analog input pins for MAX 10 build-in DECA User Manual www.terasic.com...
  • Page 29 300MHz with the soft IP of MAX 10 external memory interface solution. Figure 3-20 shows the connections between the DDR3 and MAX 10 FPGA. Table 3-11 shows the DDR3 interface pin assignments. DECA User Manual www.terasic.com May 22, 2015...
  • Page 30 DDR3 Bank Address[2] SSTL-15 Class I DDR3_CAS_n PIN_E20 DDR3 Column Address Strobe SSTL-15 Class I DDR3_CKE PIN_B22 Clock Enable pin for DDR3 SSTL-15 Class I DIFFERENTIAL 1.5-V DDR3_CK_n PIN_E18 Clock for DDR3 SSTL DECA User Manual www.terasic.com May 22, 2015...
  • Page 31 SSTL-15 Class I 3.4.7 The DECA supports a 512M-bit serial NOR flash device for non-volatile storage, user data and program. This device has a 4-bit data interface and uses 3.3V CMOS signaling standard. Connections between MAX 10 FPGA and Flash are shown in Figure 3-21.
  • Page 32 The DP838620 also provides flexibility by supporting both MII and RMII interfaces. Figure 3-22 shows the connections between the MAX 10 FPGA, Ethernet PHY, and RJ-45 connector. The pin assignment associated to Gigabit Ethernet interface is listed in Table 3-13. DECA User Manual www.terasic.com May 22, 2015...
  • Page 33 Hardware Reset Signal 2.5V NET_MDIO PIN_N8 Management Data 2.5V NET_MDC PIN_R5 Management Data Clock Reference 2.5V NET_COL PIN_R4 Interrupt Open Drain Output 2.5V NET_CRS PIN_P5 GMII Transmit Clock 2.5V NET_PCF_EN PIN_V9 GMII Transmit Clock 3.3V DECA User Manual www.terasic.com May 22, 2015...
  • Page 34 Video Data bus 1.8V HDMI_TX_D7 PIN_A19 Video Data bus 1.8V HDMI_TX_D8 PIN_C14 Video Data bus 1.8V HDMI_TX_D9 PIN_A17 Video Data bus 1.8V HDMI_TX_D10 PIN_B16 Video Data bus 1.8V HDMI_TX_D11 PIN_C15 Video Data bus 1.8V DECA User Manual www.terasic.com May 22, 2015...
  • Page 35 Mini-USB interface. Figure 3-24 shows the schematic diagram of the USB circuitry; the pin assignments for the associated interface are listed in Table 3-15. DECA User Manual www.terasic.com May 22, 2015...
  • Page 36 PIN_D8 Fault input from USB power switch 1.2V 3.4.11 The DECA provides a Mobile Industry Processor Interface (MIPI) connector, allows to implement the camera module applications. Figure 3-25 shows the connection of MIPI camera module to the MAX 10 FPGA. With a resistor networks using passive components, the transmitted signals from camera/sensor can be successfully received by MAX 10 FPGA.
  • Page 37 MIPI_LP_MD_n[1] PIN_C2 LP single-ended MIPI Data Lane 1 signal dn1 1.2V MIPI_LP_MD_p[2] PIN_B1 LP single-ended MIPI Data Lane 2 signal dp2 1.2V MIPI_LP_MD_n[2] PIN_B2 LP single-ended MIPI Data Lane 2 signal dn2 1.2V DECA User Manual www.terasic.com May 22, 2015...
  • Page 38 2.5V 3.4.12 The DECA has a low-power, reflectance-based, infrared proximity and ambient light sensor (Si1143) with I2C digital interface and programmable-event interrupt output. The Si1143 is an active optical reflectance proximity detector and ambient light sensor whose operational state is controlled through registers accessible through the I2C interface.
  • Page 39 The LM71 has 13-bit plus sign temperature resolution (0.03125°C per LSB) while operating over a temperature range of −40°C to +150°C. The LM71 temperature sensor is placed at near the heat source of DECA so that user can easily make the board temperature measurement. Figure 3-28 shows the connection of temperature sensor to MAX 10 FPGA.
  • Page 40 +-2g/+-4g/+-8g/+-16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz. Figure 3-29 shows the connection of accelerometer sensor to MAX 10 FPGA. Table 3-20 lists accelerometer sensor pin assignments. DECA User Manual www.terasic.com May 22, 2015...
  • Page 41 Micro SD card to implement external storage application. Figure 3-30 shows signals connected between the MAX 10 FPGA and Micro SD card socket. Table 3-21 lists the pin assignment of Micro SD card socket to the MAX 10 FPGA. DECA User Manual www.terasic.com May 22, 2015...
  • Page 42 1.5V SD_DAT[2] PIN_T19 Data bit 2 connected to FPGA 1.5V SD_DAT[3] PIN_R20 Data bit 3 connected to FPGA 1.5V 3.4.17 The DECA is powered by Altera’s Enpirion power solution which provides high-efficiency power DECA User Manual www.terasic.com May 22, 2015...
  • Page 43 FPGAs and SoCs. Figure 3-31 shows the positions of Altera Enpirion regulators on DECA. Figure 3-32 is the power tree of DECA. Figure 3-31 The positions of Altera Enpirion regulators DECA User Manual www.terasic.com May 22, 2015...
  • Page 44 Figure 3-32 The power tree of DECA DECA User Manual www.terasic.com May 22, 2015...

  • Page 45: Deca System Builder

    Chapter 4 DECA System Builder Need to create a custome design project but not sure where to start? We have created a DECA System Builder that can help you get started with your own design project in literally minutes. The DECA System Builder is a Windows-based utility. It is designed to help users create a Quartus II project for DECA within minutes.

  • Page 46: Using Deca System Builder

    JTAG interface using the Qaurtus II programmer. Figure 4-1 Design flow of building a project from the beginning to the end This section provides the procedures in details on how to use the DECA System Builder.  Install and Launch the DECA System Builder The DECA System Builder is located in the directory: “Tools\SystemBuilder”...
  • Page 47 Figure 4-2 The GUI of DECA System Builder  Enter Project Name Enter the project name in the circled area, as shown in Figure 4-3. The project name typed in will be assigned automatically as the name of your top-level design entity.
  • Page 48 4-5. There are two kind of pinout name. One is the default and another is MODE 7. In default pinout, the pinout name is the same as DECA schematic. If MODE 7, the pinout name is the same as the MODE 7 pinout name defined in BBB product.
  • Page 49 The “Prefix Name” is an optional feature that denotes the pin name of the daughter card assigned in your design. Users may leave this field blank.  Project Setting Management The DECA System Builder also provides the option to load a setting or save user’s current board configuration in .cfg file, as shown in Figure 4-6.
  • Page 50 Figure 4-6 Project Settings  Project Generation When users press the Generate button as shown in Figure 4-7, the DECA System Builder will generate the corresponding Quartus II files and documents, as listed in Table 4-1: DECA User Manual www.terasic.com...
  • Page 51 Figure 4-7 Generate Quartus Project Table 4-1 Files generated by the DECA System Builder Filename Description <Project name>.v Top level Verilog HDL file for Quartus II <Project name>.qpf Quartus II Project File <Project name>.qsf Quartus II Setting File <Project name>.sdc Synopsis Design Constraints file for Quartus II <Project name>.htm...

  • Page 52: Rtl Example Codes

    Chapter 5 RTL Example Codes This chapter provides examples of advanced designs implemented by RTL on the DECA board. These reference designs cover the features of peripherals connected to the FPGA, such as Humidity & Temperature measurement, G-Sensor, and HDMI output. All the associated files can be found in the directory \Demonstrations of DECA System CD The first demo is the breathing LEDs and it’s to show you how to use the FPGA to control the...
  • Page 53  Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable from the USB-Blaster II port (J10) on the DECA board to the host PC.  Power on the DECA board.

  • Page 54: User Io And Clock

    LEDs. Two 50MKZ clocks are divided by 50000000(in MAX10) to acquire 1HZ clocks and output to LEDs, LEDs blink with 1HZ. Two circular pads (B0, B1) on DECA PCB board are Capsense Touch Buttons. CY8CMBR3102 IC will process the capacitance values (which are...
  • Page 55  Quartus II v15.0  Demonstration Source Code  Project directory: User_IO  Bitstream used: DECA_User_IO.sof  Demonstration Batch File Demo batch file folder: \User_IO\demo_batch The directory includes the following files:  Batch file: test.bat DECA User Manual www.terasic.com May 22, 2015...
  • Page 56  Demonstration Setup  Quartus II v15.0 must be pre-installed to the host PC.  Connect the DECA board (J10) to the host PC with a USB cable and install the USB-Blaster II driver if necessary.  Plug the 5V adapter to DECA Board.

  • Page 57: Humidity And Temperature Measure

    A humidity/temperature sensor IC (HDC1000) embedded on DECA board can monitor environment temperature and humidity values and cash the values to the IC register. FPGA (MAX10) can read the values by I2C bus.  Function Block Diagram Figure 5-4 is the function block diagram of this demonstration. RH_TEMP module keeps sending master I2C timing to monitor (HDC1000) to read real-time temperature/humidity value.
  • Page 58  Demonstration Setup  Quartus II v15.0 must be pre-installed to the host PC.  Connect the DECA board (J10) to the host PC with a USB cable and install the USB-Blaster II driver if necessary  Plug the 5V adapter to DECA Board ...

  • Page 59: Power Monitor

    Purple box: is the actual temperature value (refer to datasheet, page14: actual temperature value= (Temperature Register / 65536) *165-40 = (27844/65536)*165 -40= 30.1=30). A power monitor IC (INA230AIRGTR) embedded on DECA board can monitor MAX10 real-time current and power. This IC can work out current/power value as multiplier and divider are embedded in it.
  • Page 60 SignalTap II. Figure 5-6 Block diagram of the Power Monitor The precision of the current value converted by INA230 depends on Calibration (CAL) register setting. Refer to following equation for CAL Register setting: DECA User Manual www.terasic.com May 22, 2015...
  • Page 61 On the DECA board, Rshunt value is 0.003 (R27 resistance). Bus Voltage (V ) and Short Voltage ) are actual measured values saved in registers. With these two values INA230 can work out current (Is = V / Rs ) and power (P = V * Is).

  • Page 62: Proximity/Ambient Light Sensor

     Demonstration Setup  Quartus II v15.0 must be pre-installed to the host PC.  Connect the DECA board (J10) to the host PC with a USB cable and install the USB-Blaster II driver if necessary  Plug the 5V adapter to DECA Board ...
  • Page 63 LEVEL_CAMP, LEVEL_CAMP will output 8bit level to LED0~LED7.When the object is closest to the light sensor IC, more LEDs(LED0~LED7) light up. On the contrary, when object gets further to DECA board, less LEDS light up.

  • Page 64: G-Sensor

     Demonstration Setup  Quartus II v15.0 must be pre-installed to the host PC.  Connect the DECA board (J10) to the host PC with a USB cable and install the USB-Blaster II driver if necessary  Plug the 5V adapter to DECA.
  • Page 65   Quartus II v15.0 must be pre-installed to the host PC.  Connect the DECA board (J10) to the host PC with a USB cable and install the USB-Blaster II driver if necessary  Plug the 5V adapter to DECA Board.

  • Page 66: Line-In Adc

     Take up DECA and tilt it left and right, two flash LEDs will moves on LED0~LED7 according the inclination value. Want to see something even more fun? You can use the built-in ADC (Analog to Digital Converter) within FPGA and the LEDs to check out the audio volume coming from the left-channel of the Line-IN audio jack.
  • Page 67 The responded digital value is stored in an unsigned 12-bit binary format with range from 0 to 4095. It is mapped to the voltage range 0V to 2.5V, as shown in Figure 5-14. DECA User Manual www.terasic.com May 22, 2015...
  • Page 68 -1.25V to 1.2V. Hence 0x800 is mapped to 0V audio input, 0xFFF is mapped to 1.25V input audio, and 0x00 is mapped to -1.25V input audio. The absolute audio voltage is first DECA User Manual www.terasic.com May 22, 2015...

  • Page 69: Hdmi Tx

     Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable from the USB-Blaster II port (J10) on the DECA board to the host PC.  Input audio into the Line-In Jack (J2) on the DECA board.
  • Page 70 The ADV7513 can accommodate from 2 to 8 channels of I2S audio at up to a 192 KHz sampling rate. The ADV7513 supports standard I2S, left-justified serial audio, and right-justified serial audio. Figure 5-16 shows the left-justified serial audio with I2S Standard Audio of 16 bit per channel. DECA User Manual www.terasic.com May 22, 2015...
  • Page 71 Table 5-2 Display Modes of the HDMI TX Demonstration Pixel Data [23:0] R[7:0] G[7:0] B[7:0]  Demonstration Source Code Quartus Project directory: HDMI_TX  Project directory: HDMI_TX  Bit stream:HDMI_TX.sof  Demonstration Batch File DECA User Manual www.terasic.com May 22, 2015...
  • Page 72  Demonstration Setup  Make sure Quartus II and USB-Blaster II driver are installed on your PC.  Connect the DECA board to the LCD monitor with the on-board HDMI connector via an HDMI cable.  Power on the DECA board .
  • Page 73 Figure 5-18 The Video pattern used in the HDMI TX Demonstration DECA User Manual www.terasic.com May 22, 2015...

  • Page 74: Nios Based Example Codes

    Can’t wait to get started with the DECA board? We provide several NIOS based examples for you to try them on the DECA board. All of the NIOS based examples can be found in the System CD under the folder Demonstrations. You are free to use them or modify these examples in your future design! There is a special capacitive touch sensor called CapSense on DECA board.
  • Page 75 NACK until it transits into Active state. When the device sends NACK from a transaction, the host is expected to repeat the DECA User Manual www.terasic.com May 22, 2015...
  • Page 76  Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable to the USB-Blaster II connector (J10) between the DECA board and the host PC.  Power on the DECA board.

  • Page 77: Temperature Sensor

    The ambient temperature information, which is collected by the built-in temperature sensor on the DECA board, can be converted into digital data by a 14-bit A/D converter. A Temp Controller is used by Nios II software to access the sensor’s registers. The C program will configure and read the registers, and then calculates the centigrade degree.
  • Page 78 Make sure Quartus II v15.0 and Nios II v15.0 are installed on your PC.  Power on the DECA board.  Connect USB Blaster II to the DECA board and install USB Blaster II driver if necessary. DECA User Manual www.terasic.com May 22, 2015...

  • Page 79: Power Monitor

     Execute the demo batch file “ DECA _TEMP.bat” under the batch file folder, DECA _TEMP \demo_batch. After Nios II program is downloaded and executed successfully, the related information will be displayed in nios2-terminal , shown in Figure 6-6. Figure 6-6 Running results of the Temperature demonstration The Power Measurement demonstration illustrates how to measure the DECA power consumption based on the built-in power measure circuit.
  • Page 80  Make sure Quartus II is installed on your PC.  Connect USB cable to the DECA board and install the USB Blaster II driver if necessary.  Execute the demo batch file DECA_Power_Monitor_Nios.bat to load the bitstream and software execution file to the FPGA.

  • Page 81: Humidity/Temperature Sensor

    I2C compatible interface. Figure 6-8 shows the block diagram of this demonstration. In this demonstration, a Nios II processor is used to achieve i2c operation and display results on the Nios II console. DECA User Manual www.terasic.com May 22, 2015...
  • Page 82 I2C function is adopted to simplify the process.  System Requirements The following items are required for this demonstration.  DECA board x1  Demonstration File Locations  Hardware project directory: Humidity_Temperature_NIOS  Bitstream used: DECA_golden_top.sof ...

  • Page 83: G-Sensor

     Make sure Quartus II and USB-Blaster II driver are installed on your PC.  Connect the USB cable to the USB Blaster II connector (J10) on the DECA board and host PC.  Input signals into the both SMA(J3 and J5) on the DECA board.
  • Page 84  Demo batch file : DECA_GSensor_Nios \demo_batch\ DECA_GSensor_Nios.bat  Demonstration Setup and Instructions  Make sure Quartus II is installed on your PC.  Connect USB cable to the DECA board and install the USB BlasterII driver if necessary. DECA User Manual www.terasic.com...

  • Page 85: Sma Adc

    The measured voltage is displayed in Nios II terminal. Figure 6-13 shows the block diagram of SMA-ADC on the DECA board. The SMA input signal goes to the amplifier circuit and then to the build-in ADC in MAX 10. The output voltage and input voltage have the following relationship: Output Voltage = (6.25V + Input Voltage)/5...
  • Page 86 Figure 6-13 Block diagram of SMA ADC The built-in ANAIN1 and ANAIN2 channels in MAX 10 on the DECA board receive signals coming out of amplifier circuits. Figure 6-14 shows the settings of Altera Modular ADC core for the first SMA input in this demonstration. “Standard sequencer with Avalon-MM sample storage”...
  • Page 87  Demonstration Setup  Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable from the USB-Blaster II port (J10) on the DECA board to the host PC. DECA User Manual www.terasic.com...

  • Page 88: Ddr3 Sdram Test By Nios Ii

     Feed signals into the SMA connectors (J3 and J5) on the DECA board.  Power on the DECA board.  Execute the demo batch file “test.bat” under the batch file folder SMA_ADC_NIOS\demo_batch.  Nios II terminal will display the voltage value of signals coming from the SMA connectors, as shown in Figure 6-15.
  • Page 89 2. Setup correct parameters in DDR3 controller dialog. 3. Perform “Analysis and Synthesis” by clicking Quartus menu: ProcessStartStart Analysis & Synthesis. 4. Run the TCL files generated by DDR3 IP by clicking Quartus menu: ToolsTCL Scripts…  Design Tools DECA User Manual www.terasic.com May 22, 2015...
  • Page 90  Power on the DECA board.  Use USB cable to connect PC and the DECA board (J10) and install USB Blaster driver if necessary.  Execute the demo batch file “test.bat” for USB-Blaster II under the batch file folder, DECA_DDR3_Nios_Test\demo_batch ...
  • Page 91 Figure 6-17 Display Progress and Result Information for the DDR3 Demonstration DECA User Manual www.terasic.com May 22, 2015...

  • Page 92: Advanced Nios Based Example Codes

    Advanced NIOS Based Example Codes Several advanced NIOS based examples for you to try them on the DECA board. All of the NIOS based examples can be found in the System CD under the folder Demonstrations. You are free to use them or modify these examples in your future design! If you don’t want to use RTL to develop HDMI Transmitter, you can try C-code to develop HDMI...
  • Page 93  Auto Hot Plug Detection The demonstration implements an interrupt-driven hot-plug detection mechanism which will automatically power on the transmitter chip when the HDMI cable is plugged into the development board and the LCD monitor is powered. DECA User Manual www.terasic.com May 22, 2015...
  • Page 94 Because our main program is stored at on-chip memory of FPGA, the program will occupy a lot of on-chip memory. So we need to modify the Optimization Level to be Size which allow developers to use memory more efficiently. Figure 7-2 shows how to set the Optimization level. DECA User Manual www.terasic.com May 22, 2015...
  • Page 95  Demo batch file folder: Demonstrations\ HDMI_TX_NIOS  Batch file: test.bat  FPGA configure file: NIOS_HDMI_TX.sof  Nios II program: HDMI_TX.elf  Demonstration Setup  Make sure Quartus II and USB-Blaster II driver are installed on your PC. DECA User Manual www.terasic.com May 22, 2015...
  • Page 96  Connect the DECA board to the LCD monitor with the on-board HDMI connector via an HDMI cable.  Power on the DECA board.  Use File Manager to locate the "HDMI_TX_NIOS\demo_batch" folder. Launch the configuration and program download process by double clicking "test.bat" batch file. This will configure the FPGA, and download the demo application to the board and start its execution.

  • Page 97: Gesture Light Sensor

    The demonstration involves certain activities that user could interact with the on-board HDMI transmitter. DECA is able to provide advanced human-machine interaction by gesture detection through the Proximity Sensing of 3 irLED (Infrared Light-Emitting Diode) and the computing chip (Si1143).
  • Page 98 0x01->0x02). JTAG UART module is used to let user dump information. Si1143 will send out interrupt signal in specific situation, so a PIO is needed to receive the interrupt signal from Si1143. Our demo shows 2 types of operations by press KEY[0] on DECA board to switch operation type.  Operation in type 1 Our default demo is Type1, running NIOS will execute PS_FORCE command to renew the data in Proximity Sensing (PS) Register of irLED.
  • Page 99  Operation in type 2 User has to switch from Type 1 to Type 2 by press KEY[0] on the DECA board. In Type 2 demo, Si1143 will read and update PS Register automatically then send out interrupt signal to NIOS when done reading and updating data.
  • Page 100  Demonstration Source Code  Project directory: Gesture_Light_Sensor_NIOS  Bit stream: Light_Sensor.sof  Demonstration Batch File  Demo batch file folder: Gesture_Light_Sensor_NIOS\demo_batch  Batch File: test.bat, test.sh  FPGA Configure File: Light_Sensor.sof  NIOS Program: Gesture_Test.elf DECA User Manual www.terasic.com May 22, 2015...

  • Page 101: Ethernet Socket Server

     Demonstration Setup  Make sure Quartus II and USB-Blaster II driver are installed on your PC.  Connect the USB cable to the USB Blaster II connector(J10) on the DECA board and host PC.  Power on the DECA board.
  • Page 102 II processor, DDR3 memory, JTAG UART, timer, Triple-Speed Ethernet, Scatter-Gather DMA controller and other peripherals etc. In the configuration page of the Altera Triple-Speed Ethernet Controller, users need to set the MAC interface as MII as shown in Figure 7-10. DECA User Manual www.terasic.com May 22, 2015...
  • Page 103 MAC control register interface clock to produce the MDC clock output on the MDIO interface. The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2.5MHz, so a host clock divisor of 40 should be used. DECA User Manual www.terasic.com May 22, 2015...
  • Page 104 Figure 7-11 MAC Options Configuration Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 7-12, click on generate. DECA User Manual www.terasic.com May 22, 2015...
  • Page 105 Figure 7-12 Qsys Builder Figure 7-13 shows the connections for programmable 10/100Mbps Ethernet operation via MII. Figure 7-13 PHY connected to the MAC via MII DECA User Manual www.terasic.com May 22, 2015...
  • Page 106 7-14. The top block contains the Nios II processor and the necessary hardware to be implemented into the DECA board. The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work. The HAL API block provides the interface for the software device drivers, while the Micro C/OS-II provides communication services to the NicheStack™...
  • Page 107 NicheStack™ TCP/IP Stack will start to run for Socket Server application. Figure 7-15 describes this demo setup and connections on DECA .The Nios II processor is running NicheStack™ on the MicroC/OS-II RTOS. Figure 7-15 System Principle Diagram...
  • Page 108  Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable from the USB-Blaster II port (J10) on the DECA board to the host PC.  Power on the DECA board.

  • Page 109: Micro Sd Card File System Read

     From the Simple Socket Server Menu, enter the commands in the telnet session. Entering a number from zero through seven, followed by a return, causes the corresponding LEDs (D0-D7) to toggle on or off on the DECA board as shown below in Figure 7-18.
  • Page 110 The DECA board provides the hardware and software needed for Micro SD Card access. In this demonstration, we will show you how to browse files stored in the root directory of a SD Card and how to read the file contents of a specific file. The Micro SD Card is required to be formatted as FAT File System in advance.
  • Page 111 LED[3:0] if it fails to parse the FAT file system or if there is no SD card found in the SD Card socket of the DECA board. If users press KEY[1] on DECA board, the program will perform the above process again.
  • Page 112  Copy SDCARD \demo_batch\test.txt files to the root directory of the SD Card.  Insert the Micro SD Card into the SD Card socket of DECA, as shown in Figure 7-21. Figure 7-21 Insert the Micro SD card into DECA ...

  • Page 113: Audio

    Figure 7-22 Running result of SD_CARD demo on DECA board This demonstration shows how to implement an audio player using the DECA board with the built-in Audio CODEC chip. This demonstration is developed based on Qsys and Eclipse. SW0 is used to Figure 7-23 configure this audio system which specify playing source to be Line-in or Beep generation.
  • Page 114  Configure audio with the slide switches as shown in Table 7-2.  Push up SW0 on the DECA board to start audio playing from LINE-IN  Push down SW0 on the DECA board to start audio playing from Beep Generation DECA User Manual www.terasic.com May 22, 2015...

  • Page 115: Usb Port Interface

    Figure 7-24 The setup for the Audio demonstration This demonstration demonstrates USB Port Interface application on DECA board using the SLS USB20SR IP with ULPI interface. In the demo the host PC can perform single word or multiple words read and write operation on the DECA board via USB interface.
  • Page 116 Windows 32 API User Guide for software application development on the top of USB device driver, and the Nios II HAL API User Guide for IP configuration on the DECA board. The host Application and drivers in the demo are pre-built, and the user can directly execute and load them.
  • Page 117  Quartus II v15.0 64-bit  Demonstration Source Code  Project directory: Demonstrations/deca_usb_ulpi Note: the USB20SR IP license is Eval version, so the *.sof file is time-limited, keep the usb blaster II cable connected during running. DECA User Manual www.terasic.com May 22, 2015...
  • Page 118  Please make sure Quartus II and USB-Blaster II driver are installed on the host PC.  Connect the USB cable from the USB-Blaster II port (J10) on the DECA board to the host PC.  Power on the DECA board.
  • Page 119 Figure 7-28 SLS USB 2.0 Device  Execute the application file to make the Word or File Write and Read Verify operation as Figure 7-29 shows. DECA User Manual www.terasic.com May 22, 2015...
  • Page 120 Figure 7-29 Word write and read Verfication Note: using the on-chip memory address range for DMA access from 0x100BDCD to 0x1020F57 and the file size for File Read and Write Verify should be within the range. DECA User Manual www.terasic.com May 22, 2015...

  • Page 121: Programming The Configuration Flash Memory

    Memory This tutorial provides comprehensive information that will help you understand how to configure DECA Board using internal configuration mode to support dual image boot . The following sections provide a quick overview of the design flow. The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode: ...
  • Page 122 5. Reconfiguration is triggered by the following actions:  Driving the nSTATUS low externally  Asserting internal or external nCONFIG low  Asserting RU_nCONFIG low DECA User Manual www.terasic.com May 22, 2015...

  • Page 123: Factory Default Dual Boot Image

    Before power on the board, users can switch which image to be loaded into MAX10 FPGA by BOOT_SEL (SW2). In addition, these two images’ corresponding Quartus II projects can be found in the Demonstrations folder on the DECA System CD. Next section will introduce how to program image file into FPGA CFM.
  • Page 124 1. Open Quartus project and choose Tools > Qsys to open new Qsys system wizard .See Figure 8-4. Figure 8-4 Qsys Menu 2. Choose Library > Basic Function> Configuration and Programming > Altera Dual Configuration to open wizard of adding Dual boot IP. See Figure 8-5. DECA User Manual www.terasic.com May 22, 2015...
  • Page 125 3. Click Finish to close the wizard and return to the window as shown in Figure 8-6. Figure 8-6 Add Dual Boot IP [2] 4. Choose dual_boot_0 and rename it to dual_boot, connect the clk and nreset to clk_0.clk and clk_0.clk_reset as shown in Figure 8-7. DECA User Manual www.terasic.com May 22, 2015...
  • Page 126 8-8. Click Save it as dual_boot.qsys and the generation start. If there is no error in the generation, the window will show successful as shown in Figure 8-9. Figure 8-8 Generate and save Qsys DECA User Manual www.terasic.com May 22, 2015...
  • Page 127 8-10. Figure 8-10 Input verilog Text 7. Add the dual_boot.qip file to the project and save the project. Secondly, the project needs to be set before the compilation. After adding dual IP successfully, DECA User Manual www.terasic.com May 22, 2015...
  • Page 128 2. Click Device and Pin Opinions to open the Device and Pin Opinions windows, and in the Configuration tab, Set the Configuration Scheme to Internal Configuration and the Configuration Mode to Dual Internal Images. Check the Option of Generate compressed bitstreams. shown in Figure 8-12. DECA User Manual www.terasic.com May 22, 2015...
  • Page 129 .sof file by internal configuration mode. Finally, So far, we have successfully obtained two image .sof files for dual boot demo according previous steps. this section describes how to generate .pof from .sof files with the internal DECA User Manual www.terasic.com May 22, 2015...
  • Page 130 4. Browse to the target directory from the File name field and specify the name of output file. 5. Click on the SOF data in the section of Input files to convert, as shown in Figure 8-14. DECA User Manual www.terasic.com May 22, 2015...
  • Page 131 Figure 8-14 Dialog of “Convert Programming Files” 6. Click Add File. 7. Select the DECA.sof of LedBreathe demo to be the sof data of Page_0. 8. Click Add Sof Page to add Page_1 and click Add File, Select the DECA_Gsensor.sof of DECA_Gsensor demo to be the .sof data of Page_1 as shown in...
  • Page 132 EPCS device with the .pof file created in Quartus II Programmer. 1. Choose Programmer from the Tools menu and the Chain.cdf window will appear. 2. Click Hardware Setup and then select the Arrow MAX 10 DECA as shown in Figure 8-16.
  • Page 133 Now, you can set the BOOT_SEL by SW2, you will find if you set BOOT_SEL=0, the Led Breathe functions would show. Power down the board, set BOOT_SEL=1, then Power on, you would find the DECA Gsensor functions show. DECA User Manual www.terasic.com...

  • Page 134: Appendix

    Add Chapter 4 and Chapter 5 V1.0 Add Chapter 6 and Chapter 7 V1.1 Add Chapter 8 V1.2 Modify Chapter 6 V1.3 Modify Chapter 8 Copyright © 2015 Terasic Inc. All rights reserved. DECA User Manual www.terasic.com May 22, 2015...

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