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Figure 3-18 Connections between the FPGA and audio CODEC
Signal Name
AUDIO_MCLK
AUDIO_BCLK
AUDIO_WCLK
AUDIO_DIN_MFP1
AUDIO_DOUT_MFP2 PIN_P18 Audio serial data bus data input/general purpose input 1.5V
AUDIO_SCLK_MFP3
AUDIO_SCL_SS_n
AUDIO_SDA_MOSI
AUDIO_MISO_MFP4
AUDIO_SPI_SELECT PIN_N22 Control mode select pin
AUDIO_RESET_n
AUDIO_GPIO_MFP5
3.4.5
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The DECA board implements two analog input SMA connectors. The analog inputs are amplified
and translated by Texas Instruments INA159 gain of 0.2 level translation difference amplifier, then
the amplifier's outputs are fed to dedicated single-ended analog input pins for MAX 10 build-in
DECA User Manual
Table 3-10 Pin Assignment of Audio CODEC
FPGA Pin
Description
No.
PIN_P14 Master output Clock
PIN_R14 Audio serial data bus (primary) bit clock
PIN_R15 Audio serial data bus (primary) word clock
Audio serial data bus data output/digital microphone
PIN_P15
output
PIN_P19 SPI serial Clock/headphone-detect output
PIN_P20 I2C Clock/SPI interface mode chip-select signal
PIN_P21 I2C Data/SPI interface mode serial data output
PIN_N21 Serial data input/General purpose input
PIN_M21 Reset signal
PIN_M22 General Purpose digital IO/CLKOUT input
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www.terasic.com
May 22, 2015
I/O Standard
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
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