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 Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)
 High speed or Full speed operation selection through Software configuration
 ULPI interface Supports CONTROL,IN and OUT endpoints
Note: for more detailed information about the USB20SR IP, Please visit the SLS website.
In this demo the Nios II embedded CPU initial and configure the USB20SR IP core as a USB
device for PC as
Figure 7-25
endpoints, which are IN (ID 1)and OUT(ID 2) with a max transmission packet size of 64 bytes. You
can find the Vendor ID is 0x1772 and the Product ID is 0x0002.
The demo also supports DMA access between USB20SR and the on-chip memory, which can
increase the system efficiency and alleviate the Nios II burden on memory access. And the DMA
access is bidirectional, which can perform write and read operation on the on-chip memory. The
on-chip memory address range for DMA access is 0x100BDCD to 0x1020F57.
User can refer to the documents from the SLS website or IP installation package. The documents
include the Qsys Tutorial for the SOPC system design, the User Guide for IP introduction,
Windows 32 API User Guide for software application development on the top of USB device
driver, and the Nios II HAL API User Guide for IP configuration on the DECA board.
The host Application and drivers in the demo are pre-built, and the user can directly execute and
load them. The recommend OS environment is 32-bits Win7 or XP.
DECA User Manual
shows. The device speed is Full, and the ULPI interface has 2
Figure 7-25 Port Interface System Block Diagram
115
www.terasic.com
May 22, 2015

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