Arrow DECA User Manual page 93

Figure 7-1 shows the system block diagram of this reference design. Our main program is NIOS
Program, and NIOS program will be stored at on-chip memory of FPGA. I2C Master formed by 2
PIO signals of (SCL and SDA) is used to configure HDMI Transmitter, proper configuration is
necessary before HDMI Transmitter successfully occupy. PLL and Audio Generator are designed to
transmit audio pattern to HDMI-transmitter, audio transmitting interface is I2S in this demo. A PIO
(HDMI Interrupt) is used to receive the interrupt signal from HDMI Transmitter. JTAG UART with
Avalon interface implements a method to communicate serial character streams between a host PC
and Qsys on FPGA, users can dump information out through JTAG UART. The default resolution
of video pattern is FULL HD generator (1920*1080p), and it can be modified by adjusting the
parameter of PLL and video pattern generator. The module "Video Pattern Generator" copes with
generating video patterns to be presented on the LCD monitor. The pattern is composed in the way
of 24-bit RGB 4:4:4 (RGB888 per color pixel without sub-sampling) color encoding, which
corresponds to the parallel encoding format defined in
Guide," as shown below.
Table 7-1 Build-in Display Modes of the HDMI TX Demonstration
Pixel Data [23:0]
17 16 15
R[7:0]
 Auto Hot Plug Detection
The demonstration implements an interrupt-driven hot-plug detection mechanism which will
automatically power on the transmitter chip when the HDMI cable is plugged into the development
board and the LCD monitor is powered.
DECA User Manual
Figure 7-1 Block Diagram of the HDMI TX Demonstration
14 13 12 11 10
G[7:0]
Table 7-1 of the "ADV7513 Hardware User's
9 8 7 6 5
B[7:0]
92
4 3 2 1 0
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May 22, 2015