Arrow DECA User Manual page 32

Figure 3-21 Connections between MAX 10 FPGA and QSPI Flash
Signal Name
FLASH_DATA[0]
FLASH_DATA[1]
FLASH_DATA[2]
FLASH_DATA[3]
FLASH_DCLK
FLASH_NCSO
3.4.8 E t h e r n
E t h e r n
The board supports 10/100 Mbps Ethernet transfer by an external Texas Instruments DP83620 PHY
chip. The DP838620 also provides flexibility by supporting both MII and RMII interfaces.
3-22 shows the connections between the MAX 10 FPGA, Ethernet PHY, and RJ-45 connector. The
pin assignment associated to Gigabit Ethernet interface is listed in
DECA User Manual
Table 3-12 Pin Assignment of QSPI Flash
FPGA Pin No.
PIN_P12
PIN_V4
PIN_V5
PIN_P10
PIN_R12
PIN_R10
e t
e t
Description
FLASH Data[0]
FLASH Data[1]
FLASH Data[2]
FLASH Data[3]
FLASH Data Clock
FLASH Chip Enable
31
Table 3-13.
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May 22, 2015
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Figure