Arrow DECA User Manual page 30

Signal Name
DDR3_A[0]
DDR3_A[1]
DDR3_A[2]
DDR3_A[3]
DDR3_A[4]
DDR3_A[5]
DDR3_A[6]
DDR3_A[7]
DDR3_A[8]
DDR3_A[9]
DDR3_A[10]
DDR3_A[11]
DDR3_A[12]
DDR3_A[13]
DDR3_A[14]
DDR3_BA[0]
DDR3_BA[1]
DDR3_BA[2]
DDR3_CAS_n
DDR3_CKE
DDR3_CK_n
DECA User Manual
Figure 3-20 Connections between the DDR3 and FPGA
Table 3-11 Pin Assignment of FPGA DDR3 Memory
FPGA Pin No. Description
PIN_E21 DDR3 Address[0]
PIN_V20 DDR3 Address[1]
PIN_V21 DDR3 Address[2]
PIN_C20 DDR3 Address[3]
PIN_Y21 DDR3 Address[4]
PIN_J14 DDR3 Address[5]
PIN_V18 DDR3 Address[6]
PIN_U20 DDR3 Address[7]
PIN_Y20 DDR3 Address[8]
PIN_W22 DDR3 Address[9]
PIN_C22 DDR3 Address[10]
PIN_Y22 DDR3 Address[11]
PIN_N18 DDR3 Address[12]
PIN_V22 DDR3 Address[13]
PIN_W20 DDR3 Address[14]
PIN_D19 DDR3 Bank Address[0]
PIN_W19 DDR3 Bank Address[1]
PIN_F19 DDR3 Bank Address[2]
PIN_E20 DDR3 Column Address Strobe
PIN_B22 Clock Enable pin for DDR3
PIN_E18 Clock for DDR3
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I/O Standard
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
DIFFERENTIAL 1.5-V
SSTL
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May 22, 2015