Arrow DECA User Manual page 33

Figure 3-22 Connections between the MAX 10 FPGA and Gigabit Ethernet
Signal Name
NET_TX_EN
NET_TX_CLK
NET_TXD[0]
NET_TXD[1]
NET_TXD[2]
NET_TXD[3]]
NET_RX_DV
NET_RX_ER
NET_RXD[0]
NET_RXD[1]
NET_RXD[2]
NET_RXD[3]
NET_RX_CLK
NET_RESET_n
NET_MDIO
NET_MDC
NET_COL
NET_CRS
NET_PCF_EN
DECA User Manual
Table 3-13 Pin Assignment of Ethernet PHY
FPGA Pin No. Description
PIN_P3 GMII and MII transmit enable
PIN_T5 GMII and MII transmit enable
PIN_U2 MII transmit data[0]
PIN_W1 MII transmit data[1]
PIN_N9 MII transmit data[2]
PIN_W2 MII transmit data[3]
PIN_P4 GMII and MII receive data valid
PIN_V1 GMII and MII receive data valid
PIN_U5 GMII and MII receive data[0]
PIN_U4 GMII and MII receive data[1]
PIN_R7 GMII and MII receive data[2]
PIN_P8 GMII and MII receive data[3]
PIN_T6 GMII and MII receive clock
PIN_R3 Hardware Reset Signal
PIN_N8 Management Data
PIN_R5 Management Data Clock Reference
PIN_R4 Interrupt Open Drain Output
PIN_P5 GMII Transmit Clock
PIN_V9 GMII Transmit Clock
32
I/O Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3.3V
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May 22, 2015