Arrow DECA User Manual page 31

DDR3_CK_p
DDR3_CS_n
DDR3_DM[0]
DDR3_DM[1]
DDR3_DQ[0]
DDR3_DQ[1]
DDR3_DQ[2]
DDR3_DQ[3]
DDR3_DQ[4]
DDR3_DQ[5]
DDR3_DQ[6]
DDR3_DQ[7]
DDR3_DQ[8]
DDR3_DQ[9]
DDR3_DQ[10]
DDR3_DQ[11]
DDR3_DQ[12]
DDR3_DQ[13]
DDR3_DQ[14]
DDR3_DQ[15]
DDR3_DQS_n[0]
DDR3_DQS_n[1]
DDR3_DQS_p[0]
DDR3_DQS_p[1]
DDR3_ODT
DDR3_RAS_n
DDR3_RESET_n
DDR3_WE_n
3.4.7 Q S P I F
Q S P I F
The DECA supports a 512M-bit serial NOR flash device for non-volatile storage, user data and
program. This device has a 4-bit data interface and uses 3.3V CMOS signaling standard.
Connections between MAX 10 FPGA and Flash are shown in
DDR3 interface pin assignments
DECA User Manual
PIN_D18 Clock p for DDR3
PIN_F22 DDR3 Chip Select
PIN_N19 DDR3 Data Mask[0]
PIN_J15 DDR3 Data Mask[1]
PIN_L20 DDR3 Data[0]
PIN_L19 DDR3 Data[1]
PIN_L18 DDR3 Data[2]
PIN_M15 DDR3 Data[3]
PIN_M18 DDR3 Data[4]
PIN_M14 DDR3 Data[5]
PIN_M20 DDR3 Data[6]
PIN_N20 DDR3 Data[7]
PIN_K19 DDR3 Data[8]
PIN_K18 DDR3 Data[9]
PIN_J18 DDR3 Data[10]
PIN_K20 DDR3 Data[11]
PIN_H18 DDR3 Data[12]
PIN_J20 DDR3 Data[13]
PIN_H20 DDR3 Data[14]
PIN_H19 DDR3 Data[15]
PIN_L15 DDR3 Data Strobe n[0]
PIN_K15 DDR3 Data Strobe n[1]
PIN_L14 DDR3 Data Strobe p[0]
PIN_K14 DDR3 Data Strobe p[1]
PIN_G22 DDR3 On-die Termination
PIN_D22 DDR3 Row Address Strobe
PIN_U19 DDR3 Reset
PIN_E22 DDR3 Write Enable
l a s h
l a s h
Figure
30
CLASS I
Differential 1.5-V SSTL
Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
SSTL-15 Class I
3-21. Table 3-12 shows the
www.terasic.com
May 22, 2015