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Figure 3-16 Connections between the power monitor chip and the MAX 10 FPGA
Signal Name
PMONITOR_I2C_SCL PIN_Y3
PMONITOR_I2C_SDA PIN_Y1
PMONITOR_ALERT
3
.
4
.
3
T
w
o
2
x
3
.
4
.
3
T
w
o
2
x
The board has two 46-pin expansion headers. The P8 header has 44 digital user pins connected
directly to the MAX 10 FPGA, the P9 header has 25 digital and 7 analog user pins connected to the
MAX 10 FPGA. The P9 header also comes with DC +5V (VCC5), DC +3.3V (VCC3P3) power
pins. The maximum power consumption allowed for a daughter card connected to one or two GPIO
ports is shown in
Table
Table 3-8 Voltage and Max. Current Limit of Expansion Header(s)
Supplied Voltage
5V
3.3V
DECA User Manual
Table 3-7 Pin Assignment of Power Monitor I2C bus
FPGA Pin No.
Description
Power Monitor SCL
Power Monitor SDA
PIN_Y4
Power Monitor ALERT
2
3
E
x
p
a
n
s
i
o
2
3
E
x
p
a
n
s
i
o
3-8.
n
H
e
a
d
e
r
s
n
H
e
a
d
e
r
s
Max. Current Limit
1A
1A
23
I/O Standard
3.3V
3.3V
3.3V
www.terasic.com
May 22, 2015
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