Standard Event Status Enable Register (Ese); Status Byte Register (Stb) - THORLABS ITC502 Operation Manual

3.8.2 Standard event status enable register (ESE)

The bits of the ESE are used to select, which bits of the ESR shall influence bit 5
(ESB) of the STB. The 8 bits of the ESE are combined with the according 8 bits of
the ESR via a wired "AND"-function. These 8 results are combined with a logical
"OR"-function, so that any "hit" leads to a logical 1 in bit 5 (ESB) of the STB. As any
bit of the STB can assert an SRQ, every event (bit of the ESR) can be used to assert
an SRQ.

3.8.3 Status byte register (STB)

The bits of this register are showing the status of the ITC5xx.
RQS
MSS
MAV
DES
EAV
FIN
The STB can be read directly with the command
can not be set. The bits are active high.
RQS: Request service message: Shows, that this device
has asserted SRQ (red via serial poll).
Master summary status: Shows that this device requests a
service (read via
"*STB"
(message available) This bit is high after a query request,
as a result "waits" in the output queue to be fetched. It is
low, if the output queue is empty.
(device error status) This bit is high after a device error
occurred. Which device errors shall set this bit is defined
with the EDE.
(error available) This bit is high as long as there are errors
in the error queue.
(command finished) This bit is high, after a command has
finished and all bits of the STB have been set.
).
The content of the STB
"*STB?".
3.8 Status reporting
ITC500 / page 93