Altera Stratix IV Device Handbook page 689

2–20
Transceiver Channel Datapath Clocking
This section describes the transmitter channel and receiver channel datapath clocking
in various configurations. Datapath clocking varies with physical coding sublayer
(PCS) configurations in different functional modes as well as channel bonding
options. This section contains:
"Transmitter Channel Datapath Clocking" on page 2–20
■
"Receiver Channel Datapath Clocking" on page 2–39
■
1
Clocking described in this section is internal to the transceiver and clock routing is
primarily performed by the Quartus II software.
f
For more information about manually picking and placing CMU and ATX PLLs, refer
to AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT
Devices.
Transmitter Channel Datapath Clocking
This section describes the transmitter channel PMA and PCS datapath clocking in
non-bonded and bonded channel configurations:
"Non-Bonded Channel Configurations" on page 2–24
■
"Bonded Channel Configurations" on page 2–27
■
■ "Non-Bonded Basic (PMA Direct) Mode Channel Configurations" on page 2–34
■ "Bonded Basic (PMA Direct) ×N Mode Channel Configurations" on page 2–36
Stratix IV Device Handbook
Volume 2: Transceivers
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
September 2012 Altera Corporation