Page 1 January Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.8...
Page 2 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 3: Table Of Contents
Ordering Information ..............1–19 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Logic Array Blocks .
Page 4 Stratix IV Operational Mode Descriptions ........
Page 5 Stratix IV PLL Hardware Overview ........
Page 6 Mixing Voltage-Referenced and Non-Voltage-Referenced Standards ..... 6–47 Chapter 7. External Memory Interfaces in Stratix IV Devices Stratix IV Device Handbook...
Page 7 Stratix IV External Memory Interface Features ........
Page 8 Hot-Socketing Feature Implementation in Stratix IV Devices ........
Page 9 Stratix IV External Power Supply Requirements ........
Page 10 Contents Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 11: Volume
Chapter Revision Dates The chapters in this document, Stratix IV Device Handbook, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Overview for the Stratix IV Device Family...
Page 12 Chapter Revision Dates Revised: February 2011 Part Number: SIV51012-3.2 Chapter 13. Power Management in Stratix IV Devices Revised: February 2011 Part Number: SIV51013-3.2 Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 13 FPGA in the market place. This section includes the following chapters: ■ Chapter 1, Overview for the Stratix IV Device Family ■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices ■ Chapter 3, TriMatrix Embedded Memory Blocks in Stratix IV Devices ■...
Page 14 I–2 Section I: Device Core Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 15 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 16: Feature Summary
Feature Summary The following list summarizes the Stratix IV device family features: ■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively ■ Dedicated circuitry to support physical layer functionality for popular serial...
Page 17: Stratix Iv Gx Devices
Chapter 1: Overview for the Stratix IV Device Family 1–3 Feature Summary Stratix IV GX Devices Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps...
Page 18: Stratix Iv E Device
Chapter 1: Overview for the Stratix IV Device Family Feature Summary Stratix IV E Device Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive. Figure 1–2 shows a high-level Stratix IV E chip view.
Page 19: Stratix Iv Gt Devices
1–5 Feature Summary Stratix IV GT Devices Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps ■...
Page 20: Architecture Features
Architecture Features The Stratix IV device family features are divided into high-speed transceiver features and FPGA fabric and I/O features. The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT devices. High-Speed Transceiver Features The following sections describe high-speed transceiver features for Stratix IV GX and GT devices.
Page 21: Diagnostic Features
PCI Express Compiler User Guide. Signal Integrity Stratix IV devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. These enhancements include: Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis ■...
Page 22: Fpga Fabric And I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features. Device Core Features Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in ■ Stratix IV E devices, efficiently packed in unique and innovative adaptive logic modules (ALMs) ■...
Page 23: Plls
■ Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT devices DPA circuitry at the receiver automatically compensates for channel-to-channel ■...
Page 24: System Integration
For more information about how to connect the PLL, external memory interfaces, I/O, high-speed differential I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines and the Stratix IV GT Device Family Pin Connection Guidelines.
Page 25 Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part 1 of 2) Feature EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Package Option ALMs 29,040 42,240 70,300 91,200 116,480 141,440 212,480 72,600 105,600...
Page 26 (4) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (5) The difference between the Stratix IV GX devices in the –2 and –2x speed grades is the number of available transceiver channels. The –2 device allows you to use the transceiver CMU blocks as transceiver channels.
Page 27 On-package decoupling reduces the need for on-board or PCB decoupling capacitors by satisfying the transient current requirements at higher frequencies. The Power Delivery Network design tool for Stratix IV devices accounts for the on-package decoupling and reflects the reduced requirements for PCB decoupling capacitors.
Page 28 Table 1–3 lists the Stratix IV GX device on-package decoupling information. Table 1–3. Stratix IV GX Device On-Package Decoupling Information Ordering Information and V (Shared) CCIO CCL_GXB CCA_L/R EP4SGX70 HF35 21uF + 2470nF 10nF per bank 100nF per transceiver block 100nF 1470nF + 147nF per side...
Page 29 Table 1–4 lists the Stratix IV E device features. Table 1–4. Stratix IV E Device Features Feature EP4SE230 EP4SE360 EP4SE530 EP4SE820 Package Pin Count 1152 1152 1517 1760 1152 1517 1760 ALMs 91,200 141,440 212,480 325,220 228,000 353,600 531,200 813,050...
Page 30 For more information about decoupling design of engineering sample (ES) devices, contact Altera Technical Support. Table 1–7 lists the Stratix IV GT device features. Table 1–7. Stratix IV GT Device Features (Part 1 of 2) Feature EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3...
Page 31 Chapter 1: Overview for the Stratix IV Device Family 1–17 Architecture Features Table 1–7. Stratix IV GT Device Features (Part 2 of 2) Feature EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4 EP4S100G5 10G Transceiver Channels (600 Mbps - 11.3 Gbps with PMA + PCS)
Page 32 1–18 Chapter 1: Overview for the Stratix IV Device Family Architecture Features Table 1–8 lists the resource counts for the Stratix IV GT devices. Table 1–8. Stratix IV GT Device Package Options 1517 Pin 1932 Pin Device (40 mm x 40 mm)
Page 33: Integrated Software Platform
MegaWizard Plug-In Manager interface that guides you through configuration of the transceiver based on your application requirements. The Stratix IV GX and GT transceivers allow you to implement low-power and reliable high-speed serial interface applications with its fully reconfigurable hardware, optimal signal integrity, and integrated Quartus II software platform.
Page 34 1–20 Chapter 1: Overview for the Stratix IV Device Family Ordering Information Figure 1–5 shows the ordering codes for Stratix IV GT devices. Figure 1–5. Stratix IV GT Device Packaging Ordering Information EP4S EP4S Family S i g n a t u r e...
Page 35 Updated “FPGA Fabric and I/O Features” on page 1–8. ■ November 2008 Updated Table 1–1. ■ Updated Table 1–2. ■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT ■ Device.” on page 1–15. July 2008 Revised “Introduction”. May 2008 Initial release.
Page 36 1–22 Chapter 1: Overview for the Stratix IV Device Family Ordering Information Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 37: Logic Array Blocks
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 38 Either Side by Columns & LABs, & from Above by Rows The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB, as shown in Figure 2–2.
Page 39 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–3 Logic Array Blocks For more information about the MLAB, refer to the chapter. Figure 2–2. Stratix IV LAB and MLAB Structure LUT-based-64 x 1 Simple dual-port SRAM...
Page 40: Lab Interconnects
2–4 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Logic Array Blocks LAB Interconnects The LAB local interconnect can drive ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs/MLABs, M9K RAM blocks, M144K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB’s local interconnect through the...
Page 41: Adaptive Logic Modules
Adaptive Logic Modules The ALM is the basic building block of logic in the Stratix IV architecture. It provides advanced features with efficient logic usage. Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers.
Page 42 2–6 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain.
Page 43 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–7 Adaptive Logic Modules Figure 2–6 shows a detailed view of all the connections in an ALM. Figure 2–6. Stratix IV ALM Connection Details syncload aclr[1:0] carry_in...
Page 44: Alm Operating Modes
2–8 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT.
Page 45: Normal Mode
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one Stratix IV ALM, or a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
Page 46 Quartus II software to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically uses the full potential of the Stratix IV ALM. The Quartus II Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources.
Page 47: Extended Lut Mode
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–11 Adaptive Logic Modules Extended LUT Mode Use extended LUT mode to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs.
Page 48: Arithmetic Mode
2–12 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders.
Page 49 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–13 Adaptive Logic Modules Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared-arithmetic mode. The two-bit carry select feature in Stratix IV devices halves the propagation delay of carry chains within the ALM.
Page 50: Shared Arithmetic Mode
2–14 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add within the ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs.
Page 51: Lut-Register Mode
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–15 Adaptive Logic Modules Similar to the carry chains, the top and bottom halves of shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality.
Page 52 2–16 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Figure 2–13 shows the ALM in LUT-register mode. Figure 2–13. ALM in LUT-Register Mode with Three-Register Capability clk [2:0] aclr [1:0] reg_chain_in datain...
Page 53: Register Chain
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–17 Adaptive Logic Modules Register Chain In addition to general routing outputs, ALMs in the LAB have register-chain outputs. Register-chain routing allows registers in the same LAB to be cascaded together. The register-chain interconnect allows the LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift-register implementation.
Page 54: Alm Interconnects
2–18 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules ALM Interconnects There are three dedicated paths between the ALMs—register cascade, carry chain, and shared arithmetic chain. Stratix IV devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions.
Page 55: Lab Power Management Techniques
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–19 Adaptive Logic Modules LAB Power Management Techniques The following techniques are used to manage static and dynamic power consumption within the LAB: ■ To save AC power, the Quartus II software forces all adder inputs low when ALM adders are not in use.
Page 56 2–20 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 57: Overview
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 58 3–2 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview Table 3–1. Summary of TriMatrix Memory Features (Part 2 of 2) Feature MLABs M9K Blocks M144K Blocks 8K × 1 16K × 8 4K × 2 64 × 8 16K ×...
Page 59: Trimatrix Memory Block Types
3–3 Overview Table 3–2 lists the capacity and distribution of the TriMatrix memory blocks in each Stratix IV family member. Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices Total Dedicated RAM Bits Total RAM Bits M144K Device...
Page 60 3–4 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview The default value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. The byte enable registers have no clear port.
Page 61: Packed Mode Support
3–5 Overview Packed Mode Support Stratix IV M9K and M144K blocks support packed mode. The packed mode feature packs two independent single-port RAMs into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block into true dual-port mode and using the MSB of the address to distinguish between the two logical RAMs.
Page 62: Address Clock Enable Support
Overview Address Clock Enable Support All Stratix IV memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable.
Page 63: Mixed Width Support
MLABs do not support mixed-width FIFO mode. Asynchronous Clear Stratix IV TriMatrix memory blocks support asynchronous clears on output latches and output registers. Therefore, if your RAM is not using output registers, you can still clear the RAM outputs using the output latch asynchronous clear.
Page 64: Error Correction Code (Ecc) Support
Overview Error Correction Code (ECC) Support Stratix IV M144K blocks have built-in support for error correction code (ECC) when in ×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in the memory array. The M144K blocks have a single-error-correction double-error-detection (SECDED) implementation.
Page 65: Memory Modes
Block Data Output Memory Modes Stratix IV TriMatrix memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations.
Page 66: Single-Port Ram Mode
3–10 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Single-Port RAM Mode All TriMatrix memory blocks support single-port mode. Single-port mode allows you to do either one-read or one-write operation at a time. Simultaneous reads and writes are not supported in single-port mode.
Page 67: Simple Dual-Port Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–11 Memory Modes Figure 3–8 shows timing waveforms for read and write operations in single-port mode with unregistered outputs. Registering the RAM’s outputs simply delays the q output by one clock cycle.
Page 68 3–12 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2) Write Port Read Port 8K × 1 4K × 2 2K × 4 1K × 8 512 ×...
Page 69 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–13 Memory Modes Figure 3–10 shows timing waveforms for read and write operations in simple dual-port mode with unregistered outputs. Registering the RAM outputs simply delays the q output by one clock cycle.
Page 70: True Dual-Port Mode
Memory Modes True Dual-Port Mode Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
Page 71 This results in unknown data being stored to that address location. No conflict resolution circuitry is built into the Stratix IV TriMatrix memory blocks. You must handle address conflicts external to the RAM block.
Page 72: Shift-Register Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Shift-Register Mode All Stratix IV memory blocks support shift register mode. Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions.
Page 73: Rom Mode
Clocking Modes ROM Mode All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the ROM contents of these blocks. The address lines of the ROM are registered on M9K and M144K blocks, but can be unregistered on MLABs. The outputs can be registered or unregistered.
Page 74: Independent Clock Mode
Design Considerations Independent Clock Mode Stratix IV TriMatrix memory blocks can implement independent clock mode for true dual-port memories. In this mode, a separate clock is available for each port (clock A and clock B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.
Page 75: Conflict Resolution
Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Read-During-Write Behavior You can customize the read-during-write behavior of the Stratix IV TriMatrix memory blocks to suit your design needs. Two types of read-during-write operations are available: same port and mixed port.
Page 76 3–20 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Design Considerations Figure 3–16 shows sample functional waveforms of same-port read-during-write behavior in don’t care mode for MLABs. Figure 3–16. MLABs Same-Port Read-During Write: Don’t Care Mode clk_a address...
Page 77: Mixed-Port Read-During-Write Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–21 Design Considerations Figure 3–18 shows sample functional waveforms of same-port read-during-write behavior in old data mode for M9K and M144K blocks. Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode...
Page 78 3–22 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Design Considerations Figure 3–20 shows a sample functional waveform of mixed-port read-during-write behavior for don’t care mode in MLABs. Figure 3–20. MLABs Mixed-Port Read-During-Write: Don’t Care Mode clk_a wraddress...
Page 79: Power-Up Conditions And Memory Initialization
You must take this into consideration when designing logic that might evaluate the initial power-up values of the MLAB memory block. For Stratix IV devices, the Quartus II software initializes the RAM cells to zero unless there is a .mif file specified.
Page 80: Power Management
Design Considerations Power Management Stratix IV memory block clock-enables allow you to control clocking of each memory block to reduce AC power consumption. Use the read-enable signal to ensure that read operations only occur when you need them to. If your design does not need...
Page 81 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 82: Stratix Iv Dsp Block Overview
Stratix IV DSP Block Overview Stratix IV DSP Block Overview Each Stratix IV device has two to seven columns of DSP blocks that implement multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift functions efficiently. Architectural highlights of the Stratix IV DSP block include: ■...
Page 83 Chapter 4: DSP Blocks in Stratix IV Devices 4–3 Stratix IV DSP Block Overview Table 4–1. Number of DSP Blocks in Stratix IV Devices (Part 2 of 2) Four High-Precision Multiplier Independent Input and Output Multiplication Operators Multiplier Adder Adder Mode...
Page 84: Stratix Iv Simplified Dsp Operation
Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation Stratix IV Simplified DSP Operation In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in Equation 4–1 Figure 4–2.
Page 85 Chapter 4: DSP Blocks in Stratix IV Devices 4–5 Stratix IV Simplified DSP Operation Following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the alternative functions per half block, as shown in Equation 4–2...
Page 86 To support commonly found FIR-like structures efficiently, a major addition to the DSP block in Stratix IV devices is the ability to propagate the result of one half block to the next half block completely within the DSP block without additional soft logic overhead.
Page 87 4–7 Stratix IV Simplified DSP Operation Figure 4–5 shows a top-level view of the Stratix IV DSP block. Figure 4–6 on page 4–9 shows a more detailed top-level view of the DSP block. Figure 4–5. Stratix IV Full DSP Block...
Page 88: Stratix Iv Operational Modes Overview
Stratix IV Operational Modes Overview Stratix IV Operational Modes Overview You can use each Stratix IV DSP block in one of five basic operational modes. Table 4–2 lists the five basic operational modes and the number of multipliers that you can implement within a single DSP block, depending on the mode.
Page 89: Stratix Iv Dsp Block Resource Descriptions
Chapter 4: DSP Blocks in Stratix IV Devices 4–9 Stratix IV DSP Block Resource Descriptions Stratix IV DSP Block Resource Descriptions The DSP block consists of the following elements: ■ Input register bank ■ Four two-multiplier adders Pipeline register bank ■...
Page 90: Input Registers
4–10 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions Input Registers All of the DSP block registers are triggered by the positive edge of the clock signal and are cleared after power up. Each multiplier operand can feed an input register or go directly to the multiplier, bypassing the input registers.
Page 91 Chapter 4: DSP Blocks in Stratix IV Devices 4–11 Stratix IV DSP Block Resource Descriptions A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) can be driven from general routing or from the cascade...
Page 92: Multiplier And First-Stage Adder
(LE) resources required, avoids routing congestion, and results in predictable timing. The first multiplier in every half DSP block (top- and bottom-half) in Stratix IV devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure 4–6 on page...
Page 93: Pipeline Register Stage
Chapter 4: DSP Blocks in Stratix IV Devices 4–13 Stratix IV DSP Block Resource Descriptions Each half block has its own signa and signb signal. Therefore, all of the data A inputs feeding the same half DSP block must have the same sign representation. Similarly, all of the data B inputs feeding the same half DSP block must have the same sign representation.
Page 94: Rounding And Saturation Stage
72-bit banks to support 36 × 36 output results. The outputs of the different stages in the Stratix IV devices are routed to the output registers through an output selection unit. Depending on the operational mode of the...
Page 95: Stratix Iv Operational Mode Descriptions
■ aclr[3..0] Stratix IV Operational Mode Descriptions This section contains an explanation of different operational modes in Stratix IV devices. Independent Multiplier Modes In independent input and output multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers.
Page 96 4–16 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–8. 18-Bit Independent Multiplier Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round overflow (1) aclr[3..0] output_saturate dataa_0[17..0] result_0[ ] datab_0[17..0] dataa_1[17..0] result_1[ ] datab_1[17..0]...
Page 97 Chapter 4: DSP Blocks in Stratix IV Devices 4–17 Stratix IV Operational Mode Descriptions Figure 4–9. 12-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[11..0] result_0[ ] datab_0[11..0] dataa_1[11..0] result_1[ ] datab_1[11..0] dataa_2[11..0] result_2[ ] datab_2[11..0]...
Page 98 4–18 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–10. 9-Bit Independent Multiplier Mode Shown for a Half Block clock[3..0] signa ena[3..0] aclr[3..0] signb dataa_0[8..0] result_0[ ] datab_0[8..0] dataa_1[8..0] result_1[ ] datab_1[8..0] dataa_2[8..0] result_2[ ] datab_2[8..0]...
Page 99: Bit Multiplier
DSP block and is implemented in the DSP block automatically by selecting 36 × 36 mode. Stratix IV devices can have up to two 36-bit multipliers per DSP block (one 36-bit multiplier per half DSP block). The...
Page 100: Double Multiplier
Stratix IV Operational Mode Descriptions Double Multiplier You can configure the Stratix IV DSP block to efficiently support a signed or unsigned 54 × 54-bit multiplier that is required to compute the mantissa portion of an IEEE double-precision floating point multiplication. You can build a 54 × 54-bit multiplier using basic 18 ×...
Page 101 Chapter 4: DSP Blocks in Stratix IV Devices 4–21 Stratix IV Operational Mode Descriptions Figure 4–13. Unsigned 54 × 54 Multiplier for a Half-DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] Two Multiplier "0" Adder Mode "0" dataa[53..36] datab[53..36] Double Mode dataa[35..18]...
Page 102: Two-Multiplier Adder Sum Mode
4–22 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Two-Multiplier Adder Sum Mode In a two-multiplier adder configuration, the DSP block can implement four 18-bit two-multiplier adders (2 two-multiplier adders per half DSP block). You can configure the adders to take the sum or difference of two multiplier outputs.
Page 103 Chapter 4: DSP Blocks in Stratix IV Devices 4–23 Stratix IV Operational Mode Descriptions Figure 4–14. Two-Multiplier Adder Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate overflow (1) dataa_0[17..0] datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0]...
Page 104: X 18 Complex Multiply
4–24 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–15. Loopback Mode for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round output_saturate aclr[3..0] zero_loopback overflow (1) dataa_0[17..0] loopback datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0]...
Page 105 Chapter 4: DSP Blocks in Stratix IV Devices 4–25 Stratix IV Operational Mode Descriptions To implement this complex multiplication within the DSP block, the real part ((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a ×...
Page 106: Four-Multiplier Adder
4–26 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Four-Multiplier Adder In the four-multiplier adder configuration shown in Figure 4–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block).
Page 107: High-Precision Multiplier Adder Mode
Chapter 4: DSP Blocks in Stratix IV Devices 4–27 Stratix IV Operational Mode Descriptions Four-multiplier adder mode supports the rounding and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block.
Page 108 4–28 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–18. High-Precision Multiplier Adder Configuration signa clock[3..0] signb ena[3..0] aclr[3..0] overflow (1) dataA[0:17] dataB[0:17] dataA[0:17] <<18 dataB[18:35] result[ ] dataC[0:17] dataD[0:17] dataC[0:17] <<18 dataD[18:35] Half-DSP Block...
Page 109: Multiply Accumulate Mode
Chapter 4: DSP Blocks in Stratix IV Devices 4–29 Stratix IV Operational Mode Descriptions Multiply Accumulate Mode In multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. The output of the DSP block is looped back to the...
Page 110: Shift Modes
32-bit rotator or barrel shifter, ROT[N] You can switch between these modes using the dynamic rotate and shift control signals. You can use shift mode in a Stratix IV device by using a soft embedded processor such ® as Nios II to perform the dynamic shift and rotate operation.
Page 111 Chapter 4: DSP Blocks in Stratix IV Devices 4–31 Stratix IV Operational Mode Descriptions Figure 4–20. Shift Operation Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] rotate shift_right aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0]...
Page 112: Rounding And Saturation Mode
Rounding and saturation functions are often required in DSP arithmetic. Use rounding to limit bit growth and its side effects; use saturation to reduce overflow and underflow side effects. Two rounding modes are supported in Stratix IV devices: ■ Round-to-nearest-integer mode ■...
Page 113 800000001h 800000000h Stratix IV devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0]) for the rounding and saturate logic unit, providing higher flexibility. These 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as...
Page 114: Dsp Block Control Signals
(A × B)]] DSP Block Control Signals The Stratix IV DSP block is configured using a set of static and dynamic signals. You can configure the DSP block dynamic signals. You can set the signals to toggle or not toggle at run time.
Page 115: Software Support
DSP block-wide asynchronous clear signals (active low). aclr2 aclr3 Total Count per Full Block Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design—instantiation and inference. Both methods use the following Quartus II megafunctions: ■ lpm_mult ■...
Page 116: Software Support
4–36 Chapter 4: DSP Blocks in Stratix IV Devices Software Support For more information, refer to the “Synthesis” section in volume 1 of the Quartus II Handbook. Document Revision History Table 4–10 lists the revision history for this chapter. Table 4–10. Document Revision History...
Page 117 Chapter 4: DSP Blocks in Stratix IV Devices 4–37 Software Support February 2011 Altera Corporation Stratix IV Device Handbook Volume 1...
Page 118 4–38 Chapter 4: DSP Blocks in Stratix IV Devices Software Support Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 119: Clock Networks In Stratix Iv Devices
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 120 Stratix IV devices have up to 32 dedicated single-ended clock pins or 16 dedicated differential clock pins (CLK[0..15]p and CLK[0..15]n) that can drive either the GCLK or RCLK networks. These clock pins are arranged on the four sides of the Stratix IV device, as shown in Figure 5–1...
Page 121: Global Clock Networks
Clock Networks in Stratix IV Devices Global Clock Networks Stratix IV devices provide up to 16 GCLKs that can drive throughout the device, serving as low-skew clock sources for functional blocks such as adaptive logic modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks, and PLLs.
Page 122: Regional Clock Networks
The Stratix IV device IOEs and internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals;...
Page 123 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–5 Clock Networks in Stratix IV Devices Figure 5–3. RCLK Networks (EP4S40G2, EP4S100G2, EP4SGX180, and EP4SGX230 Devices) CLK[12..15] RCLK[54..63] RCLK[44..53] RCLK[0..5] RCLK[38..43] Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31]...
Page 124: Periphery Clock Networks
(PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK networks. PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Stratix IV device. Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices) CLK[12..15]...
Page 125 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–7 Clock Networks in Stratix IV Devices Figure 5–6. PCLK Networks (EP4S40G2, EP4S100G2, EP4SE230, EP4SE360, EP4SGX180, EP4SGX230, EP4SGX290, and EP4SGX360 Devices) CLK[12..15] PCLK[0..10] PCLK[77..87] PCLK[11..21] PCLK[66..76] Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 PCLK[22..32]...
Page 126 5–8 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Figure 5–8. PCLK Networks (EP4SE820 Device) CLK[12..15] PCLK[0..15] PCLK[116..131] PCLK[16..32] PCLK[99..115] CLK[0..3] CLK[8..11] PCLK[33..49] PCLK[82..98] PCLK[50..65] PCLK[66..81] CLK[4..7] Stratix IV Device Handbook September 2012 Altera Corporation...
Page 127: Clock Sources Per Quadrant
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row. Clock Regions Stratix IV devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in the entire device. You can use these clock resources to form the following types of clock regions: ■...
Page 128: Clock Network Sources
Clock Network Sources In Stratix IV devices, clock input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks. For connectivity between dedicated pins CLK[0..15] and the GCLK and RCLK networks, refer to Table 5–2...
Page 129: Pll Clock Outputs
Table 5–3 lists the connectivity between the dedicated clock input pins and RCLKs in Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network. Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)
Page 130: Clock Input Connections To The Plls
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a global clock is used. (2) For the availability of the clock input pins in each device density, refer to the “Stratix IV Device Pin-Out Files” section of the...
Page 131: Clock Output Connections
I/O bank as the PLL used. Clock Output Connections PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK networks. For Stratix IV PLL connectivity to GCLK networks, refer to Table 5–5.
Page 132: Clock Control Block
5–14 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs (Part 2 of 2) PLL Number Clock Resource — — — —...
Page 133 (.sof or .pof) generated by the Quartus II software. You can power down the Stratix IV clock networks using both static and dynamic approaches. When a clock network is powered down, all the logic fed by the clock network is in off-state, thereby reducing the overall power consumption of the device.
Page 134 5–16 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.
Page 135: Clock Enable Signals
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof). In Stratix IV devices, the clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when you are not using a PLL.
Page 136: Clock Source Control For Plls
Clock Source Control for PLLs The clock input to Stratix IV PLLs comes from clock input multiplexers. The clock multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK and RCLK networks, or from dedicated connections between adjacent top/bottom and left/right PLLs.
Page 137: Cascading Plls
GCLK or RCLK network. Using this path reduces clock jitter when cascading PLLs. Stratix IV GX devices allow cascading the left and right PLLs to transceiver PLLs (CMU PLLs and receiver CDRs).
Page 138 — — EP4SGX530 F1760 F1932 All Stratix IV PLLs have the same core analog structure with only minor differences in the features that are supported. Table 5–8 lists the features of top/bottom and left/right PLLs in Stratix IV devices. Table 5–8. PLL Features in Stratix IV Devices (Part 1 of 2)
Page 139 (4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs. (5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix IV °...
Page 140 5–22 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Figure 5–18 shows the location of PLLs in Stratix IV devices. Figure 5–18. PLL Locations in Stratix IV Devices Top/Bottom PLLs Top/Bottom PLLs CLK[12..15]...
Page 141: Stratix Iv Pll Hardware Overview
There are a number of components that comprise a PLL to achieve this phase alignment. Stratix IV PLLs align the rising edge of the input reference clock to a feedback clock using the phase-frequency detector (PFD). The falling edges are determined by the duty-cycle specifications.
Page 142: Pll Clock I/O Pins
(1) The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs. (2) This is the VCO post-scale counter K. (3) The FBOUT port is fed by the M counter in Stratix IV PLLs. You can drive the GCLK or RCLK inputs using an output from another PLL, a...
Page 143 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–25 PLLs in Stratix IV Devices Figure 5–20 shows the clock I/O pins associated with the top and bottom PLLs. Figure 5–20. External Clock Outputs for Top and Bottom PLLs...
Page 144 I/O Features in Stratix IV Devices chapter. Stratix IV PLLs can also drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not need external PLL clocking.
Page 145: Pll Control Signals
Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL.
Page 146: Clock Feedback Modes
Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Clock Feedback Modes Stratix IV PLLs support up to six different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. Table 5–9 lists the clock feedback modes supported by the Stratix IV device PLLs.
Page 147: Source Synchronous Mode
IOE input register. Figure 5–22 shows an example waveform of the clock and data in this mode. Altera recommends source synchronous mode for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard.
Page 148: Source-Synchronous Mode For Lvds Compensation
5–30 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Source-Synchronous Mode for LVDS Compensation The goal of source-synchronous mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180°...
Page 149: Normal Mode
ZDB mode is supported on all Stratix IV PLLs. When using Stratix IV PLLs in ZDB mode, along with single-ended I/O standards, to ensure phase alignment between the CLK pin and the external clock output (CLKOUT) pin, you must instantiate a bi-directional I/O pin in the design to serve as the feedback path connecting the FBOUT and FBIN ports of the PLL.
Page 150: External Feedback Mode
5–32 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices When using ZDB mode, to avoid signal reflection, do not place board traces on the bi-directional I/O pin. Figure 5–26. ZDB Mode in Stratix IV PLLs inclk ÷n...
Page 151: Clock Multiplication And Division
Clock Multiplication and Division Each Stratix IV PLL provides clock synthesis for PLL output ports using M/(N* post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match f (M/N).
Page 152: Post-Scale Counter Cascading
ALTPLL megafunction. Post-Scale Counter Cascading Stratix IV PLLs support post-scale counter cascading to create counters larger than 512. This is automatically implemented in the Quartus II software by feeding the output of one C counter into the input of the next C counter, as shown in Figure 5–30.
Page 153: Programmable Duty Cycle
(PVT). You can phase-shift the output clocks from the Stratix IV PLLs in either of these two resolutions: Fine resolution using VCO phase taps ■...
Page 154 CLK1 d0-2 CLK2 You can use coarse- and fine-phase shifts to implement clock delays in Stratix IV devices. Stratix IV devices support dynamic phase-shifting of VCO phase taps only. You can reconfigure the phase shift any number of times. Each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly.
Page 155: Programmable Bandwidth
5–37 PLLs in Stratix IV Devices Programmable Bandwidth Stratix IV PLLs provide advanced control of the PLL bandwidth using the PLL loop’s programmable characteristics, including loop filter and charge pump. Background PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter.
Page 156: Implementation
PLL output. A low-bandwidth PLL filters out reference clock jitter but increases lock time. Stratix IV PLLs allow you to control the bandwidth over a finite range to customize the PLL characteristics for a particular application.
Page 157: Spread-Spectrum Tracking
However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the PLL. Stratix IV PLLs can track a spread-spectrum input clock as long as it is within input-jitter tolerance specifications. Stratix IV devices cannot internally generate spread-spectrum clocks.
Page 158: Automatic Clock Switchover
PLL may lose lock after the switchover is completed and needs time to re-lock. Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.
Page 159 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–41 PLLs in Stratix IV Devices In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. When they are asserted, the clock sense block has detected that the corresponding clock input has stopped toggling.
Page 160 5–42 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Figure 5–36 shows a clock switchover waveform controlled by clkswitch. In this case, both clock sources are functional and inclk0 is selected as the reference clock;...
Page 161: Manual Clock Switchover
For more information about PLL software support in the Quartus II software, refer to Phase-Locked Loop (ALTPLL) Megafunction User Guide. Guidelines When implementing clock switchover in Stratix IV PLLs, use the following guidelines: ■ Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 100% (2×) of each other.
Page 162: Pll Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In Stratix IV PLLs, you can reconfigure both the counter settings and phase-shift the PLL output clock in real time. You can also change the charge pump and loop-filter components, which dynamically affects PLL bandwidth.
Page 163: Pll Reconfiguration Hardware Implementation
Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–45 PLLs in Stratix IV Devices PLL Reconfiguration Hardware Implementation The following PLL components are reconfigurable in real time: Pre-scale counter (n) ■ ■ Feedback counter (m) ■ Post-scale output counters (C0 - C9) ■...
Page 164 5–46 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Table 5–10 lists how these signals can be driven by the PLD logic array or I/O pins. Table 5–10. Real-Time PLL Reconfiguration Ports PLL Port Name...
Page 165: Post-Scale Counters (C0 To C9)
Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–47 PLLs in Stratix IV Devices Figure 5–40 shows a functional simulation of the PLL reconfiguration feature. Figure 5–40. PLL Reconfiguration Waveform (LSB) (MSB) SCANDATA SCANCLK SCANCLKENA D0_old Dn_old SCANDATAOUT...
Page 166: Scan Chain Description
■ Scan Chain Description The length of the scan chain varies for different Stratix IV PLLs. The top and bottom PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right PLLs have seven post-scale counters and a 180-bit scan chain.
Page 167 (1) Left and right PLLs have the same scan-chain order. The post-scale counters end at C6. Figure 5–42 shows the scan-chain bit-order sequence for post-scale counters in all Stratix IV PLLs. Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs DATAIN rbypass DATAOUT...
Page 168: Charge Pump And Loop Filter
Stratix IV PLLs. Table 5–12. Charge Pump Current Bit Settings CP[2] CP[1] CP[0] Decimal Value for Setting Table 5–13 lists the possible settings for loop-filter resistor (R) values for Stratix IV PLLs. Table 5–13. Loop-Filter Resistor Bit Settings LFR[4] LFR[3] LFR[2] LFR[1]...
Page 169: Bypassing A Pll
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9 counters) factor of one. Table 5–15 lists the settings for bypassing the counters in Stratix IV PLLs. Table 5–15. PLL Counter Settings PLL Scan Chain Bits [0..8] Settings...
Page 170 5–52 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Table 5–16. Dynamic Phase-Shifting Control Signals (Part 2 of 2) Signal Name Description Source Destination Free running clock from the core used in combination with PHASESTEP to...
Page 171 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–53 PLLs in Stratix IV Devices You can repeat dynamic phase-shifting indefinitely. For example, in a design where the VCO frequency is set to 1000 MHz and the output clock frequency is 100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180°, which is a phase shift of 5 ns.
Page 172: Pll Specifications
■ Minor text edits. ■ Updated Table 5–1 and Table 5–7. ■ Updated “Clock Networks in Stratix IV Devices”, “Periphery Clock Networks”, and ■ “Cascading PLLs” sections. Added Figure 5–5, Figure 5–6, Figure 5–7, Figure 5–8, and Figure 5–9. ■...
Page 173 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–55 PLLs in Stratix IV Devices Table 5–18. Document Revision History (Part 2 of 2) Date Version Changes Updated Table 5–1 and Table 5–7. ■ April 2009 Updated Figure 5–3 and Figure 5–4.
Page 174 5–56 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 175 ■ Chapter 7, External Memory Interfaces in Stratix IV Devices ■ Chapter 8, High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Page 176 II–2 Section II: I/O Interfaces Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 177 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 178: I/O Standards Support
I/O standards Stratix IV devices support, as well as the typical applications. These devices support V voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V. CCIO Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2) I/O Standard Application 3.3-V LVTTL/LVCMOS General purpose 2.5-V LVCMOS...
Page 179: I/O Standards And Voltage Levels
6–1: (1) The 3.3-V LVTTL/LVCMOS standard is supported using V at 3.0 V. CCIO (2) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19. For more information about transceiver supported I/O standards, refer to the Transceiver Architecture in Stratix IV Devices chapter.
Page 180 6–4 Chapter 6: I/O Features in Stratix IV Devices I/O Standards Support Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (Part 2 of 3) CCIO CCPD Standard Input Operation Output Operation (Board I/O Standard (Pre-Driver (Input Ref...
Page 181: I/O Banks
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without on-chip R support. (3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19.
Page 182 6–6 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–1. Stratix IV E Devices I/0 Banks Bank 8A Bank 8B Bank 7B Bank 8C Bank 7C Bank 7A I/O banks 8A, 8B, and 8C support all I/O banks 7A, 7B, and 7C support all...
Page 183 It is a graphical representation only. (9) Stratix IV devices do not support the PCI clamp diode when V is 1.2 V, 1.5 V, or 1.8 V.
Page 184: Modular I/O Banks
I/O pins available in each I/O bank. In Stratix IV devices, the maximum number of I/O banks per side is either four or six, depending on the device density. When migrating between devices with a different number of I/O banks per side, it is the middle or “B”...
Page 185 Chapter 6: I/O Features in Stratix IV Devices 6–9 I/O Banks Figure 6–4 through Figure 6–16 show the number of I/O pins and packaging information for different sets of available devices. They show the top view of the silicon die that corresponds to a reverse view for flip chip packages. They are graphical representations only.
Page 186 6–10 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–6. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1517-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A Bank 6B...
Page 187 Chapter 6: I/O Features in Stratix IV Devices 6–11 I/O Banks Figure 6–8. Number of I/Os in Each Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin FineLine BGA Package Number of Number Transceiver of I/Os Channels Bank...
Page 188 6–12 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–10. Number of I/Os in Each Bank in EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A Bank 1C...
Page 189 Chapter 6: I/O Features in Stratix IV Devices 6–13 I/O Banks Figure 6–12. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A...
Page 190 6–14 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–13. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A...
Page 191 Chapter 6: I/O Features in Stratix IV Devices 6–15 I/O Banks Figure 6–14. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A...
Page 192 6–16 Chapter 6: I/O Features in Stratix IV Devices I/O Banks The information in Figure 6–15 Figure 6–16 applies to Stratix IV GX and GT devices. Figure 6–15. Number of I/Os in Each Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine...
Page 193: I/O Structure
(1) There are two additional PMA-only transceiver channels in each transceiver bank. I/O Structure The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate or DDR transfer.
Page 194 6–18 Chapter 6: I/O Features in Stratix IV Devices I/O Structure ■ On-chip series termination without calibration ■ On-chip parallel termination with calibration On-chip differential termination ■ ■ PCI clamping diode I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (OE) path for handling the OE signal to the output buffer.
Page 195: V I/O Interface
When using the Stratix IV device as a transmitter, you can use slow slew rate and series termination to limit overshoot and undershoot at the I/O pins, but they are not required.
Page 196: High-Speed Differential I/O With Dpa Support
Programmable Current Strength The output buffer for each Stratix IV device I/O pin has a programmable current strength control for certain I/O standards. Use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane.
Page 197: Programmable Slew Rate Control
Programmable Slew Rate Control The output buffer for each Stratix IV device regular- and dual-function I/O pin has a programmable output slew-rate control that you can configure for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems.
Page 198: Programmable I/O Delay
High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices chapter. Programmable Output Buffer Delay Stratix IV devices support delay chains built inside the single-ended output buffer, as shown in Figure 6–17 on page 6–18. The delay chains can independently control the...
Page 199: Programmable Pull-Up Resistor
Interfaces and DPA in Stratix IV Devices chapter. MultiVolt I/O Interface The Stratix IV architecture supports the MultiVolt I/O interface feature that allows the Stratix IV devices in all packages to interface with systems of different supply voltages. You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply, depending on the output requirements.
Page 200: On-Chip Termination Support And I/O Termination Schemes
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use an internal clamping diode for column I/O pins.
Page 201 Stratix IV devices support driver-impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce reflections. Stratix IV devices support on-chip series termination for single-ended I/O standards (Figure 6–18).
Page 202: On-Chip Series Termination With Calibration
On-Chip Termination Support and I/O Termination Schemes On-Chip Series Termination with Calibration Stratix IV devices support on-chip series termination with calibration in all banks. The on-chip series termination calibration circuit compares the total impedance of the I/O buffer to the external 25-  ±1% or 50-  ±1% resistors connected to the RUP and RDN pins and dynamically enables or disables the transistors until they match.
Page 203: Left-Shift Series Termination Control
HSTL-12 Class II — Left-Shift Series Termination Control Stratix IV devices support left-shift series termination control. You can use left-shift series termination control to get the calibrated OCT R with half of the impedance value of the external reference resistors connected to the RUP and RDN pins. This feature is useful in applications that require both 25-...
Page 204: On-Chip Parallel Termination With Calibration
On-Chip Termination Support and I/O Termination Schemes On-Chip Parallel Termination with Calibration Stratix IV devices support on-chip parallel termination with calibration in all banks. On-chip parallel termination with calibration is only supported for input configuration of input and bidirectional pins. Output pin configurations do not support on-chip parallel termination with calibration.
Page 205: Expanded On-Chip Series Termination With Calibration
HSTL-12 40–60 20–60 Dynamic On-Chip Termination Stratix IV devices support on and off dynamic termination, both series and parallel, for a bidirectional I/O in all I/O banks. Figure 6–21 shows the termination schemes supported in Stratix IV devices. Dynamic parallel termination is enabled only when the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Page 206 50  parallel OCT on the input buffer of a bidirectional pin and calibrated 40  series OCT on the output buffer because these would require two separate calibration blocks with different RUP and RDN resistor values. Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices VCCIO VCCIO Transmitter Receiver 100 Ω...
Page 207: Summary Of Oct Assignments
Chapter 6: I/O Features in Stratix IV Devices 6–31 On-Chip Termination Support and I/O Termination Schemes LVDS Input OCT (R Stratix IV devices support OCT for differential LVDS input buffers with a nominal resistance value of 100  , as shown in Figure 6–22. Differential OCT R...
Page 208: Oct Calibration
Table 6–10 lists the OCT calibration blocks in Banks 1A through 4C. Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 1 of 2) Bank Number of Device...
Page 209 Chapter 6: I/O Features in Stratix IV Devices 6–33 OCT Calibration Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 2 of 2) Bank Number of Device OCT Blocks — — — —...
Page 210: Sharing An Oct Calibration Block On Multiple I/O Banks
6–34 Chapter 6: I/O Features in Stratix IV Devices OCT Calibration Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 2 of 2) Bank Number of Device OCT Blocks — — — —...
Page 211: Oct Calibration Block Modes Of Operation
Chapter 6: I/O Features in Stratix IV Devices 6–35 OCT Calibration For example, Figure 6–23 shows a group of I/O banks that has the same V CCIO voltage. If a group of I/O banks has the same V voltage, you can use one OCT CCIO calibration block to calibrate the group of I/O banks placed around the periphery.
Page 212: User Mode
6–36 Chapter 6: I/O Features in Stratix IV Devices OCT Calibration User Mode In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to calibrate and serially transfer calibration codes from each OCT calibration block to any I/O.
Page 213: Oct Calibration
Chapter 6: I/O Features in Stratix IV Devices 6–37 OCT Calibration OCT Calibration Figure 6–25 shows user mode signal-timing waveforms. To calibrate OCT block[N] (where N is a calibration block number), you must assert ENAOCT one cycle before asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before the ENASER[N] signal is asserted.
Page 214: Example Of Using Multiple Oct Calibration Blocks
6–38 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Example of Using Multiple OCT Calibration Blocks Figure 6–26 shows a signal timing waveform for two OCT calibration blocks doing R and R calibration. Calibration blocks can start calibrating at different times by asserting the ENASER signals at different times.
Page 215 Chapter 6: I/O Features in Stratix IV Devices 6–39 Termination Schemes for I/O Standards In Stratix IV devices, you cannot use series and parallel OCT simultaneously. For more information, refer to “Dynamic On-Chip Termination” on page 6–29. Figure 6–27. SSTL I/O Standard Termination...
Page 216 6–40 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Figure 6–28. HSTL I/O Standard Termination HSTL Class II Termination HSTL Class I V TT V TT V TT 50 Ω 50 Ω 50 Ω External On-Board 50 Ω...
Page 217: Differential I/O Standards Termination
Chapter 6: I/O Features in Stratix IV Devices 6–41 Termination Schemes for I/O Standards Differential I/O Standards Termination Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18, HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS. Figure 6–29 through Figure 6–35 show the details of various differential I/O terminations on these devices.
Page 218 6–42 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Figure 6–30. Differential HSTL I/O Standard Termination Termination Differential HSTL Class II Differential HSTL Class I V TT V TT V TT V TT V TT V TT 50 Ω...
Page 219: Lvds
LVDS requires a 100- termination resistor between the two signals at the input buffer. Stratix IV devices provide an optional 100- differential termination resistor in the device using on-chip differential termination.
Page 220: Differential Lvpecl
Termination Schemes for I/O Standards Differential LVPECL In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on column and row I/O banks. LVPECL output operation is not supported in Stratix IV devices. LVDS input buffers are used to support LVPECL input operation. AC coupling is required when the LVPECL common-mode voltage of the output buffer is higher than the LVPECL input common-mode voltage.
Page 221: Rsds
Termination Schemes for I/O Standards RSDS Stratix IV devices support the RSDS output standard with data rates up to 230 Mbps using LVDS output buffer types. For transmitters, use two single-ended output buffers with the external one- or three-resistor networks in the column I/O bank, as...
Page 222: Mini-Lvds
Chapter 6: I/O Features in Stratix IV Devices Design Considerations Mini-LVDS Stratix IV devices support the mini-LVDS output standard with data rates up to 340 Mbps using LVDS output buffer types. For transmitters, use two single-ended output buffers with external one- or three-resistor networks, as shown in Figure 6–35.
Page 223: Non-Voltage-Referenced Standards
6–47 Design Considerations Non-Voltage-Referenced Standards Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one , either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any CCIO number of input signals with different I/O standard assignments if it meets the V...
Page 224 6–48 Chapter 6: I/O Features in Stratix IV Devices Design Considerations Document Revision History Table 6–13 lists the revision history for this chapter. Table 6–13. Document Revision History (Part 1 of 2) Date Version Changes Updated the “Programmable Slew Rate Control”...
Page 225 Chapter 6: I/O Features in Stratix IV Devices 6–49 Design Considerations Table 6–13. Document Revision History (Part 2 of 2) Date Version Changes Updated “Modular I/O Banks” on page 6–7. ■ November 2008 Updated Figure 6–3 and Figure 6–21. ■...
Page 226 6–50 Chapter 6: I/O Features in Stratix IV Devices Design Considerations Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 227 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 228 (1) You can bypass each register block. (2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Stratix IV IOE. (3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read and write operations.
Page 229: Memory Interfaces Pin Support
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to indicate that the read data is ready to be captured. This section describes how Stratix IV devices support all these different pins.
Page 230 CQn pin for complementary read-data strobe and clock operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and CQn pins.
Page 231 I/O standards required to support DDR3, DDR2, DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices. The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode ×32/×36.
Page 232 7–6 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 2 of 3) Device Package Side ×4 ×8/×9 ×16/×18 ×32/×36 Refer to: Left/Right...
Page 233 You cannot use these groups if you use the Stratix IV calibrated OCT feature. (3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to “Combining...
Page 234 7–8 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–3. Number of DQS/DQ Groups per Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8C...
Page 235 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–9 Memory Interfaces Pin Support Figure 7–4. Number of DQS/DQ Groups per Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7A I/O Bank 8A...
Page 236 7–10 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–5. Number of DQS/DQ Groups per Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package I/O Bank 7C I/O Bank 8A I/O Bank 8C...
Page 237 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–11 Memory Interfaces Pin Support Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine BGA Package I/O Bank 7A I/O Bank 8A...
Page 238 7–12 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the 1152-Pin FineLine BGA Package I/O Bank 7A (3)
Page 239 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–13 Memory Interfaces Pin Support Figure 7–8. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B I/O Bank 8A...
Page 240 7–14 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–9. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 241 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–15 Memory Interfaces Pin Support Figure 7–10. Number of DQS/DQ Groups per Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 242 7–16 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–11. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1517-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B I/O Bank 8A...
Page 243 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–17 Memory Interfaces Pin Support Figure 7–12. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 244 7–18 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–13. Number of DQS/DQ Groups per Bank in EP4SE530 and EP4SE820 Devices in the 1517-pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 245 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–19 Memory Interfaces Pin Support Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B...
Page 246 7–20 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–15. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 247 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–21 Memory Interfaces Pin Support Figure 7–16. Number of DQS/DQ Groups per Bank in EP4SE530 Devices in the 1760-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 248 7–22 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 249 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–23 Memory Interfaces Pin Support Figure 7–18. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B...
Page 250 Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose up to four ×4 DQS/DQ groups, depending on your configuration scheme. The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY, respectively, where X indicates the DQS/DQ grouping number and Y indicates whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.
Page 251 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–25 Memory Interfaces Pin Support The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin table. The numbering scheme starts from the top-left corner of the device going counter-clockwise in a die-top view.
Page 252: Combining ×16/×18 Dqs/Dq Groups For A ×36 Qdr Ii+/Qdr Ii Sram Interface
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in the FPGA. This is the only connection on the board that you need to change for this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV devices also apply for this implementation.
Page 253: Rules To Combine Groups
Table 7–3 lists the possible combinations to use two ×16/×18 DQS/DQ groups to form a ×32/×36 group on Stratix IV devices lacking a native ×32/×36 DQS/DQ group. Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 1 of 2)
Page 254 (3) Although it is possible to combine the ×16/×18 DQS/DQ groups from I/O banks 1A and 1C, 2A and 2C, 5A and 5C, and 6A and 6C, Altera does not recommend this due to the size of the package. Similarly, crossing a bank number (for example, combining groups from I/O banks 6C and 5C) is not supported in this package.
Page 255: Stratix Iv External Memory Interface Features
The ALTMEMPHY megafunction allows you to use these external memory interface features and helps set up the physical interface (PHY) best suited for your system. This section describes each Stratix IV device feature that is used in external memory interfaces from the DQS phase-shift circuitry, DQS logic block, leveling multiplexers, and dynamic OCT control block.
Page 256 7–30 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Figure 7–21 shows how the DQS phase-shift circuitry is connected to the DQS/CQ and CQn pins in the device where memory interfaces are supported on all sides of the Stratix IV device.
Page 257 There are a maximum of four DLLs in a Stratix IV device, located in each corner of the device. These four DLLs support a maximum of four unique frequencies, with each DLL running at one frequency.
Page 258 Stratix IV External Memory Interface Features Figure 7–22 shows the DLL and I/O bank locations in Stratix IV devices from a die-top view if all sides of the device support external memory interfaces. Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
Page 259 Table 7–5 through Table 7–17 lists the available DLL reference clock input resources for the Stratix IV device family. When you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to No Compensation to achieve better performance or the Quartus II software changes it automatically.
Page 260 7–34 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–6. DLL Reference Clock Input for EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right) (Corner)
Page 261 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–35 Stratix IV External Memory Interface Features Table 7–8. DLL Reference Clock Input for EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package (with 24 Transceivers) CLKIN CLKIN (Top/Bottom) (Left/Right)
Page 262 7–36 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–10. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right)
Page 263 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–37 Stratix IV External Memory Interface Features Table 7–12. DLL Reference Clock Input for EP4SE530 and EP4SE820 Devices in the 1517- and 1760-Pin FineLine BGA Packages CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom)
Page 264 7–38 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–14. DLL Reference Clock Input for EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom)
Page 265 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–39 Stratix IV External Memory Interface Features Table 7–16. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right)
Page 266 7–40 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Figure 7–23 shows a simple block diagram of the DLL. The input reference clock goes into the DLL to a chain of up to 16 delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock.
Page 267: Phase Offset Control
Chapter 7: External Memory Interfaces in Stratix IV Devices 7–41 Stratix IV External Memory Interface Features There are eight different frequency modes for the Stratix IV DLL, as listed in Table 7–18. Each frequency mode provides different phase shift selections. In frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to implement the phase-shift delay.
Page 268 7–42 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features You can use either a static phase offset or a dynamic phase offset to implement the additional phase shift. The available additional phase shift is implemented in 2’s: complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and...
Page 269: Dqs Logic Block
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7–5 on page 7–33 through Table 7–17 on page 7–39. (2) The dqsenable signal can also come from the Stratix IV FPGA fabric.
Page 270: Dqs Delay Chain
7–44 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features DQS Delay Chain DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ and CQn signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.
Page 271: Dqs Postamble Circuitry
DQS is in a postamble state do not affect the DQ IOE registers. In addition to the dedicated postamble register, Stratix IV devices also have an HDR block inside the postamble enable circuitry. Use these registers if the controller is running at half the frequency of the I/Os.
Page 272: Leveling Circuitry
FPGA from the memory is also staggered in a similar way. Stratix IV FPGAs have leveling circuitry to address these two situations. There is one leveling circuitry per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each has one leveling circuitry).
Page 273 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–47 Stratix IV External Memory Interface Features Figure 7–28 Figure 7–29 show the Stratix IV write- and read-leveling circuitry. Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers Write clk Write-Leveled DQS Clock...
Page 274: Dynamic On-Chip Termination Control
7–48 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and write-leveling during the initialization process. For more information about the ALTMEMPHY megafunction, refer to the...
Page 275: I/O Element Registers
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout. (9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn signals are automatically inverted.
Page 276 Circuitry” on page 7–46. Figure 7–32 shows the registers available in the Stratix IV output and output-enable paths. The path is divided into the HDR block, resynchronization registers, and output and output-enable registers. The device can bypass each block of the output and output-enable path.
Page 277 Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers Half Data Rate to Single Data Rate Output-Enable Registers Alignment Registers (4) From Core (2) Double Data Rate Output-Enable Registers From Core (2) OE Reg A Half Data Rate to Single Data Rate Output Registers...
Page 278: Delay Chain
Delay Chain Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the DQS logic blocks. You can control the delay chain setting through the I/O or the DQS configuration block output.
Page 279 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–53 Stratix IV External Memory Interface Features Figure 7–34 shows the delay chains in an I/O block. Figure 7–34. Delay Chains in an I/O Block rtena D5 OCT D5 Output- (outputdelaysetting1 +...
Page 280: I/O Configuration Block And Dqs Configuration Block
7–54 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features I/O Configuration Block and DQS Configuration Block The I/O configuration block and the DQS configuration block are shift registers that you can use to dynamically change the settings of various device configuration bits.
Page 281 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–55 Stratix IV External Memory Interface Features Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2) Bit Name 34..36 octdelaysetting2[0..2] enadataoutbypass enadqsenablephasetransferreg enaoctphasetransferreg enaoutputphasetransferreg enainputphasetransferreg resyncinputphaseinvert dqsenablectrlphaseinvert dqoutputphaseinvert dqsoutputphaseinvert Document Revision History Table 7–21...
Page 282 7–56 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–21. Document Revision History (Part 2 of 2) Date Version Changes Updated the “Memory Interfaces Pin Support” and “Combining ×16/×18 DQS/DQ Groups ■...
Page 283: Overview
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 284 ■ Reduced swing differential signaling (RSDS) ■ In the Stratix IV device family, I/Os are divided into row and column I/Os. Figure 8–1 shows I/O bank support for the Stratix IV device family. The row I/Os provide dedicated SERDES circuitry.
Page 285: Locations Of The I/O Banks
LVDS interface has the Use External PLL option enabled. Locations of the I/O Banks Stratix IV I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that supports high-speed differential I/Os is located in banks in the right and left side of the device.
Page 286: Lvds Channels
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS Channels Figure 8–3 shows a high-level chip overview of the Stratix IV GT and GX devices. Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices General Purpose General Purpose I/O and Memory...
Page 287 LVDS I/Os supported in Stratix IV E devices. You can design the LVDS I/Os as true LVDS buffers or emulated LVDS buffers, as long as the combination of the two do not exceed the maximum count.
Page 288 Table 8–3 Table 8–4 list the maximum number of row and column LVDS I/Os supported in Stratix IV GT devices. Table 8–3. LVDS Channels Supported in Stratix IV GT Device Row I/O Banks Device 1517-pin FineLine BGA 1932-pin FineLine BGA...
Page 289 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–7 LVDS Channels Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks (Part 2 of 2) 1152-Pin 780-Pin 1152-Pin 1517-Pin 1760-Pin 1932-Pin Device FineLine BGA...
Page 290: Lvds Serdes
8–8 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS SERDES LVDS SERDES Figure 8–4 shows a transmitter and receiver block diagram for the LVDS SERDES circuitry in the left and right banks. This diagram shows the interface signals of the transmitter and receiver data path.
Page 291: Altlvds Port List
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–9 ALTLVDS Port List ALTLVDS Port List Table 8–7 lists the interface signals for an LVDS transmitter and receiver. Table 8–7. Port List of the LVDS Interface (ALTLVDS)
Page 292 8–10 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices ALTLVDS Port List Table 8–7. Port List of the LVDS Interface (ALTLVDS) (Part 2 of 3) Input / Port Name Description Output LVDS Receiver Interface Signals Input LVDS receiver serial data input port.
Page 293: Differential Transmitter
Guide. Differential Transmitter The Stratix IV transmitter has a dedicated circuitry to provide support for LVDS signaling. The dedicated circuitry consists of a differential buffer, a serializer, and left and right PLLs that can be shared between the transmitter and receiver. The differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels.
Page 294 8–12 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at serial data rate) generated from PLL_Lx (left PLL) or PLL_Rx (right PLL) clocks the load and shift registers.
Page 295 Left/Right LVDS_LOAD_EN You can bypass the Stratix IV serializer to support DDR (×2) and SDR (×1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode.
Page 296 8–14 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter Programmable V and Programmable Pre-Emphasis Stratix IV LVDS transmitters support programmable pre-emphasis and programmable V . Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line.
Page 297: Programmable Vod
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–15 Differential Transmitter Pre-emphasis is an important feature for high-speed transmission. Without pre-emphasis, the output current is limited by the V setting and the output impedance of the driver. At high frequency, the slew rate may not be fast enough to reach full V before the next edge, producing pattern-dependent jitter.
Page 298: Programmable Pre-Emphasis
8–16 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter Programmable Pre-Emphasis Four different settings are allowed for pre-emphasis from the Assignment Editor for each LVDS output channel. Table 8–9 lists the assignment name and its possible values for programmable pre-emphasis in the Quartus II software Assignment Editor.
Page 299: Differential Receiver
Figure 8–12 shows the hardware blocks of the Stratix IV receiver. The receiver has a differential buffer and left and right PLLs that can be shared between the transmitter and receiver, a DPA block, a synchronizer, a data realignment block, and a deserializer. The differential buffer can receive LVDS, mini-LVDS, and RSDS signal levels, which are statically set in the Quartus II software Assignment Editor.
Page 300: Differential I/O Termination
8–18 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock and the received serial data to compensate skew. In DPA mode, the DPA circuitry automatically chooses the best phase to compensate for the skew between the source synchronous clock and the received serial data.
Page 301: Receiver Hardware Blocks
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–19 Differential Receiver Figure 8–13 shows device on-chip termination. Figure 8–13. On-Chip Differential I/O Termination Stratix IV Differential LVDS Receiver with On-Chip 100 Ω Termination Transmitter = 50 Ω...
Page 302: Synchronizer
8–20 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver The DPA block continuously monitors the phase of the incoming serial data and selects a new clock phase if needed. You can prevent the DPA from selecting a new clock phase by asserting the optional RX_DPLL_HOLD port, which is available for each channel.
Page 303 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–21 Differential Receiver ■ Valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN. Figure 8–15 shows receiver output (RX_OUT) after one bit slip pulse with the deserialization factor set to 4.
Page 304: Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,...
Page 305 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–23 Differential Receiver When using non-DPA receivers, you must drive the PLL from a dedicated and compensated clock input pin. Compensated clock inputs are dedicated clock pins in the same I/O bank as the PLL.
Page 306: Dpa Mode
8–24 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver DPA Mode Figure 8–19 shows the DPA mode datapath, where all the hardware blocks mentioned “Receiver Hardware Blocks” on page 8–19 are active. The DPA block chooses the best possible clock (DPA_diffioclk) from the eight fast clocks sent by the left and right PLL.
Page 307: Soft-Cdr Mode
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–25 Differential Receiver Soft-CDR Mode The Stratix IV LVDS channel offers soft-CDR mode to support the Gigabit Ethernet and SGMII protocols. A receiver PLL uses the local clock source for reference. Figure 8–20 shows the soft-CDR mode datapath.
Page 308: Lvds Interface With The Use External Pll Option Enabled
You can use every LVDS channel in soft-CDR mode and can drive the FPGA fabric using the periphery clock network in the Stratix IV device family. The rx_dpa_locked signal is not valid in soft-CDR mode because the DPA continuously changes its phase to track PPM differences between the upstream transmitter and the local receiver input reference clocks.
Page 309 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–27 LVDS Interface with the Use External PLL Option Enabled Table 8–10. Signal Interface Between ALTPLL and ALTLVDS_TX and ALTLVDS_RX Megafunctions (Part 2 of 2) From the ALTPLL...
Page 310 8–28 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS Interface with the Use External PLL Option Enabled Example 8–1 shows how to generate three output clocks using an ALTPLL megafunction. Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction LVDS data rate = 1 Gbps;...
Page 311: Left And Right Plls (Pll_Lx And Pll_Rx)
Left and Right PLLs (PLL_Lx and PLL_Rx) The Stratix IV device family contains up to eight left and right PLLs with up to four PLLs located on the left side and four on the right side of the device. The left PLLs can support high-speed differential I/O banks on the left side;...
Page 312: Stratix Iv Clocking
PLL clocking in the Stratix IV device family. For more information about PLL clocking restrictions, refer to “Differential Pin Placement Guidelines” on page 8–38. Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs Corner Corner PLL_R1 PLL_L1...
Page 313: Source-Synchronous Timing Budget
This section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for the Stratix IV device family, and how to use these timing parameters to determine a design’s maximum performance.
Page 314 8–32 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget For other serialization factors, use the Quartus II software tools to find the bit position within the word. Table 8–11 lists the bit positions after deserialization.
Page 315: Transmitter Channel-To-Channel Skew
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–33 Source-Synchronous Timing Budget Transmitter Channel-to-Channel Skew Transmitter channel-to-channel skew (TCCS) is an important parameter based on the Stratix IV transmitter in a source synchronous differential interface. This parameter is used in receiver skew margin calculation.
Page 316 8–34 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget Figure 8–27 shows the relationship between the RSKM, TCCS, and the receiver’s SW. You must calculate the RSKM value to decide whether or not data can be sampled properly by the LVDS receiver with the given data rate and device.
Page 317 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–35 Source-Synchronous Timing Budget For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing Analyzer.
Page 318 8–36 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget Figure 8–29 shows the setting parameters for the Set Input Delay option. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
Page 319 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–37 Source-Synchronous Timing Budget 4. Select the LVDS receiver serial input ports (from the list) according to the input delay you set. Click OK. 5. In the Set Input Delay window, set the appropriate values in the Input Delay Options section and Delay value.
Page 320: Differential Pin Placement Guidelines
Guidelines for DPA-Enabled Differential Channels The Stratix IV device family has differential receivers and transmitters in I/O banks on the left and right sides of the device. Each receiver has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
Page 321 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–39 Differential Pin Placement Guidelines You do not need a separation if a single left and right PLL is driving the DPA-enabled channels as well as DPA-disabled channels.
Page 322: Using Both Center Left And Right Plls
8–40 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Using Both Center Left and Right PLLs You can use both center left and right PLLs to drive DPA-enabled channels simultaneously, as long as they drive these channels in their adjacent banks only, as...
Page 323 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–41 Differential Pin Placement Guidelines Figure 8–33. Invalid Placement of DPA-Enabled Differential I/Os Driven by Both Center Left and Right PLLs DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled...
Page 324: Guidelines For Dpa-Disabled Differential Channels
Differential Pin Placement Guidelines Guidelines for DPA-Disabled Differential Channels When you use DPA-disabled channels in the left and right banks of a Stratix IV device, you must adhere to the guidelines in the following sections. When using non-DPA receivers, you must drive the PLL from a dedicated and compensated clock input pin.
Page 325 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–43 Differential Pin Placement Guidelines Figure 8–34. Corner and Center Left and Right PLLs Driving DPA-Disabled Differential I/Os in the Same Bank Corner Left/Right Corner Left/ Right Reference...
Page 326 8–44 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Figure 8–35. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven by the Corner and Center Left and Right PLLs...
Page 327: Using Both Center Left And Right Plls
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–45 Differential Pin Placement Guidelines Using Both Center Left and Right PLLs You can use both center left and right PLLs simultaneously to drive DPA-disabled channels on upper and lower differential banks. Unlike DPA-enabled channels, the center left and right PLLs can drive cross-banks.
Page 328 8–46 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Document Revision History Table 8–12 lists the revision history for this chapter. Table 8–12. Document Revision History (Part 1 of 2) Date Version...
Page 329 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–47 Differential Pin Placement Guidelines Table 8–12. Document Revision History (Part 2 of 2) Date Version Changes Updated Figure 8–2, Figure 8–3, Figure 8–21, Figure 8–34. ■ Removed Figure 8–31.
Page 330 8–48 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 331 Section III. System Integration This section includes the following chapters: Chapter 9, Hot Socketing and Power-On Reset in Stratix IV Devices ■ ■ Chapter 10, Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices ■ Chapter 11, SEU Mitigation in Stratix IV Devices ■...
Page 332 III–2 Section III: System Integration Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 333: Stratix Iv Hot-Socketing Specifications
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 334: Stratix Iv Devices Can Be Driven Before Power Up
In a hot-socketing situation, the Stratix IV device’s output buffers are turned off during system power up or power down. Also, the Stratix IV device does not drive out until the device is configured and working within the recommended operating conditions.
Page 335: Hot-Socketing Feature Implementation In Stratix Iv Devices
) and keeps the I/O pins tri-stated until the device is in user mode. CCPGM CCPD The weak pull-up resistor (R) in the Stratix IV input/output element (IOE) keeps the I/O pins from floating. The 3.0-V tolerance control circuit permits the I/O pins to be driven by 3.0 V before the V...
Page 336: Power-On Reset Circuitry
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices Power-On Reset Circuitry Power-On Reset Circuitry When power is applied to a Stratix IV device, a POR event occurs if the power supply reaches the recommended operating range within the maximum power supply ramp time (t ).
Page 337: Power-On Reset Specifications
CCBAT no affect on the device configuration. The POR specification is designed to ensure that all the circuits in the Stratix IV device are at certain known states during power up. The POR signal pulse width is programmable using the PORSEL input pin. When the PORSEL pin is connected to GND, the POR delay time is 100 to 300 ms.
Page 338 ■ Updated the introduction and the “Stratix IV Hot-Socketing Specifications”, “Insertion or ■ Removal of a Stratix IV Device from a Powered-Up System”, “Hot-Socketing Feature Implementation in Stratix IV Devices”, “Power-On Reset Circuitry”, and “Power-On Reset Specifications” sections. March 2010 Updated Table 9–1 and Table 9–2.
Page 339: Overview
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 340: Configuration Devices
® Altera serial configuration devices support a single-device and multi-device configuration solution for Stratix IV devices and are used in the fast AS configuration scheme. Serial configuration devices offer a low-cost, low pin-count configuration solution. For information about serial configuration devices, refer to the...
Page 341 Table 10–1: (1) Stratix IV devices only support fast AS configuration. You must use either EPCS64 or EPCS128 devices to configure a Stratix IV device in fast AS mode. (2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
Page 342: Configuration Features
If your system already contains a common flash interface (CFI) flash memory, you can use it for Stratix IV device configuration storage as well. The MAX II parallel flash loader (PFL) feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and provides the logic to control configuration from the flash memory device to the Stratix IV device.
Page 343: Power-On Reset Circuit
CCPD below the threshold voltage. In Stratix IV devices, a pin-selectable option (PORSEL) is provided that allows you to select between the standard POR time or fast POR time. When PORSEL is driven low, the standard POR time is 100 ms < T <...
Page 344: Fast Passive Parallel Configuration
DCLK Note to Figure 10–1: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V must be CCPGM high enough to meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 345 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–7 Fast Passive Parallel Configuration After power-up, the Stratix IV device goes through a POR. The POR delay depends on the PORSEL pin setting. When PORSEL is driven low, the standard POR time is 100 ms < T <...
Page 346 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Fast Passive Parallel Configuration In Stratix IV devices, the initialization clock source is either the internal oscillator or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization.
Page 347 Stratix IV device when you use the decompression and/or design security features. two clock cycles after the last data byte was latched into the Stratix IV device when ■...
Page 348 DCLK Note to Figure 10–2: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough CCPGM to meet the V specification of the I/O standard on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 349 DCLK Notes to Figure 10–3: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 350: Fpp Configuration Timing
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins depends on the dual-purpose pin settings.
Page 351 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–13 Fast Passive Parallel Configuration Table 10–4. FPP Timing Parameters for Stratix IV Devices (Part 2 of 2) (Note Minimum Maximum Symbol Parameter Units Stratix IV Stratix IV...
Page 352 (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins depends on the dual-purpose pin settings.
Page 353 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–15 Fast Passive Parallel Configuration Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features Enabled (Note (Part 2 of 2)
Page 354: Fpp Configuration Using A Microprocessor
Fast Active Serial Configuration (Serial Configuration Devices) In the fast AS configuration scheme, Stratix IV devices are configured using a serial configuration device. These configuration devices are low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor.
Page 355: Vccpgm Pins
3.3 V power supply to power the EPCS device. The EPCS device and the VCCPGM pins on the Stratix IV device may share the same 3.0 V power supply. After power-up, the Stratix IV devices go through a POR. The POR delay depends on the PORSEL pin setting.
Page 356 (DATA) pin, which connects to the DATA0 input of the Stratix IV devices. After all the configuration bits are received by the Stratix IV device, it releases the open-drain CONF_DONE pin, which is pulled high by an external 10-k resistor.
Page 357 STATUS When the Stratix IV device is in user mode, you can initiate reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin must be low for at least 2 s. When nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Page 358 10–7: (1) Connect the pull-up resistors to V at a 3.0-V supply. CCPGM (2) Connect the repeater buffers between the Stratix IV master and slave device(s) for . This is to prevent potential signal DATA[0] DCLK integrity and clock skew problems.
Page 359 The same copy of the .sof configures the master Stratix IV device and all remaining slave devices concurrently. All Stratix IV devices must be the same density and package. To configure four identical Stratix IV devices with the same .sof, set up the chain as shown in Figure 10–8.
Page 360: Estimating Active Serial Configuration Time
(1) Connect the pull-up resistors to V at a 3.0-V supply. CCPGM (2) Connect the repeater buffers between the Stratix IV master and slave device(s) for DATA[0] and DCLK. This is to prevent potential signal integrity and clock skew problems. Estimating Active Serial Configuration Time Active serial configuration time is dominated by the time it takes to transfer data from the serial configuration device to the Stratix IV device.
Page 361: Programming Serial Configuration Devices
During in-system programming, the download cable disables device access to the AS interface by driving the nCE pin high. Stratix IV devices are also held in reset by a low level on nCONFIG. After programming is complete, the download cable releases nCE...
Page 362 10–24 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Fast Active Serial Configuration (Serial Configuration Devices) For more information about the USB-Blaster download cable, refer to the USB-Blaster Download Cable User Guide. For more information about the ByteBlaster II cable, refer...
Page 363: Guidelines For Connecting Serial Configuration Devices On An As Interface
ASDO Passive Serial Configuration You can program a PS configuration for Stratix IV devices using an intelligent host, such as a MAX II device or microprocessor with flash memory, or a download cable. In the PS scheme, an external host (a MAX II device, embedded processor, or host PC) controls configuration.
Page 364: Ps Configuration Using A Max Ii Device As An External Host
MSEL0 Note to Figure 10–10: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V must be CCPGM high enough to meet the V specification of the I/O on the device and the external host. Altera recommends powering...
Page 365 Whenever the nCONFIG line is released high, ensure that the first DCLK and DATA are not driven unintentionally. The Stratix IV device receives configuration data on the DATA0 pin and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Page 366 Quartus II software from the General tab of the Device and Pin Options dialog box) is turned on, the Stratix IV device releases nSTATUS after a reset time-out period (a maximum of 500 s). After nSTATUS is released and pulled high by a pull-up resistor, the MAX II device can try to reconfigure the target device without needing to pulse nCONFIG low.
Page 367 DCLK Note to Figure 10–11: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM (2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
Page 368 DCLK Notes to Figure 10–12: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM (2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
Page 369: Ps Configuration Timing
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay. (3) After power-up, before and during configuration, CONF_DONE is low.
Page 370: Ps Configuration Using A Microprocessor
USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable. After power-up, Stratix IV devices go through a POR. The POR delay depends on the PORSEL pin setting. When PORSEL is driven low, the standard POR time is 100 ms <...
Page 371 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–33 Passive Serial Configuration The configuration cycle consists of three stages—reset, configuration, and initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration in this scheme, the download cable generates a low-to-high transition on the nCONFIG pin.
Page 372 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Passive Serial Configuration You can use a download cable to configure multiple Stratix IV devices by connecting each device’s nCEO pin to the subsequent device’s nCE pin. The first device’s nCE pin is connected to GND, while its nCEO pin is connected to the nCE of the next device in the chain.
Page 373: Jtag Configuration
Stratix IV devices during PS configuration, PS configuration is terminated and JTAG configuration begins. You cannot use the Stratix IV decompression or design security features if you are configuring your Stratix IV device when using JTAG-based configuration. A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST.
Page 374 10–36 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices JTAG Configuration During JTAG configuration, you can download data to the device on the PCB through the USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable. Configuring devices through a cable is similar to programming devices in-system, except you must connect the TRST pin to V .
Page 375 Signal Description On all Stratix IV devices in the chain, nCE must be driven low by connecting it to GND, pulling it low using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or PS configuration chains, the nCE pins must be connected to GND during JTAG configuration or JTAG must be configured in the same order as the configuration chain.
Page 376 10–38 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices JTAG Configuration Table 10–8. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2) Signal Description Driven high by connecting to V , pulling up using a resistor, or driven high by...
Page 377 JTAG configured. You can place other Altera devices that have JTAG support in the same JTAG chain for device programming and configuration.
Page 378: Jam Stapl
Notes to Figure 10–18: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. must be high enough to meet the V specification of the I/O on the device.
Page 379 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–41 Device Configuration Pins Table 10–9. Stratix IV Configuration Pin Summary (Part 2 of 2) (Note 1) Description Input/Output Dedicated Powered By Configuration Mode Input — All modes except JTAG...
Page 380 You must connect these pins properly on your board for successful configuration. Some of these pins may not be required for your configuration schemes. Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 1 of 4) Configuration Pin Name...
Page 381 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–43 Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 2 of 4) Configuration Pin Name User Mode Pin Type Description Scheme Three-bit configuration input that sets the Stratix IV device configuration scheme.
Page 382 10–44 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 3 of 4) Configuration Pin Name User Mode Pin Type Description Scheme...
Page 383 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–45 Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 4 of 4) Configuration Pin Name User Mode Pin Type Description Scheme...
Page 384 10–46 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Device Configuration Pins Table 10–11 lists the optional configuration pins. If these optional configuration pins are not enabled in the Quartus II software, they are available as general-purpose user I/O pins.
Page 385 (typically 25 k  ). If you plan to use the SignalTap ® embedded logic array analyzer, you must connect the JTAG pins of the Stratix IV device to a JTAG header on your board. Table 10–12. Dedicated JTAG Pins...
Page 386: Configuration Data Decompression
Preliminary data indicates that compression typically reduces the configuration bitstream size by 30% to 55% based on the designs used. Stratix IV devices support decompression in the FPP (when using a MAX II device or microprocessor + flash), fast AS, and PS configuration schemes. The Stratix IV decompression feature is not available in the JTAG configuration scheme.
Page 387 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–49 Configuration Data Decompression 3. In the Configuration settings tab, turn on Generate compressed bitstreams (as shown in Figure 10–19). Figure 10–19. Enabling Compression for Stratix IV Bitstreams in Compiler Settings You can also enable compression when creating programming files from the Convert Programming Files window.
Page 388: Remote System Upgrades
In a multi-device FPP configuration chain (with a MAX II device or microprocessor + flash), all Stratix IV devices in the chain must either enable or disable the decompression feature. You cannot selectively enable the compression feature for each device in the chain because of the DATA and DCLK relationship.
Page 389: Functional Description
Stratix IV devices have remote system upgrade processes that involve the following steps: 1. A Nios II processor (or user logic) implemented in the Stratix IV device logic array receives new configuration data from a remote location. The connection to the...
Page 390 10–52 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Remote System Upgrades Figure 10–21 shows the steps required for performing remote configuration updates. (The numbers in Figure 10–21 coincide with the steps just mentioned.) Figure 10–21. Functional Diagram of Stratix IV Remote System Upgrade...
Page 391: Enabling Remote Update
10–62. Enabling Remote Update You can enable remote update for Stratix IV devices in the Quartus II software before design compilation (in the Compiler Settings menu). In remote update mode, the auto-restart configuration after error option is always enabled. To enable remote update in the project’s compiler settings, in the Quartus II software, follow these...
Page 392: Configuration Image Types
Additionally, remote update mode features a user watchdog timer that determines the validity of an application configuration. When a Stratix IV device is first powered up in remote update mode, it loads the factory configuration located at page zero (page registers PGM[23:0] = 24'b0). Always store the factory configuration image for your system at page address zero.
Page 393 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–55 Remote System Upgrade Mode The factory image is user-designed and contains soft logic to: ■ Process any errors based on status information from the dedicated remote system...
Page 394 10–56 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Remote System Upgrade Mode The user watchdog timer is automatically disabled for factory configurations. For more information about the user watchdog timer, refer to “User Watchdog Timer” on page 10–61.
Page 395: Dedicated Remote System Upgrade Circuitry
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–57 Dedicated Remote System Upgrade Circuitry Dedicated Remote System Upgrade Circuitry This section describes the implementation of the Stratix IV remote system upgrade dedicated circuitry. The remote system upgrade circuitry is implemented in hard logic.
Page 396: Remote System Upgrade Registers
10–58 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Dedicated Remote System Upgrade Circuitry Remote System Upgrade Registers The remote system upgrade block contains a series of registers that store the page addresses, watchdog timer settings, and status information.
Page 397: Remote System Upgrade Status Register
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–59 Dedicated Remote System Upgrade Circuitry The application-not-factory (AnF) bit indicates whether the current configuration loaded in the Stratix IV device is the factory configuration or an application configuration.
Page 398: Remote System Upgrade State Machine
Table 10–16: (1) Logic array reconfiguration forces the system to load the application configuration data into the Stratix IV device. This occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. Remote System Upgrade State Machine...
Page 399 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–61 Dedicated Remote System Upgrade Circuitry The remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded.
Page 400: User Watchdog Timer
10–62 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Dedicated Remote System Upgrade Circuitry User Watchdog Timer The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. The system uses the timer to detect functional errors after an application configuration is successfully loaded into the Stratix IV device.
Page 401: Quartus Ii Software Support
The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Stratix IV device logic. This implementation is suitable for designs that implement the factory configuration functions using a Nios II processor or user logic in the device.
Page 402: Design Security
Stratix IV devices using the advanced encryption standard (AES). It also covers the new security modes available in Stratix IV devices. As Stratix IV devices continue play a role in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering.
Page 403: Stratix Iv Security Protection
Security Against Copying The security key is securely stored in the Stratix IV device and cannot be read out through any interfaces. In addition, as configuration file read-back is not supported in Stratix IV devices, the design information cannot be copied.
Page 404: Stratix Iv Design Security Solution
10–19: (1) Key programming is carried out using the JTAG interface. You can program the non-volatile key to the Stratix IV device without an external battery. Also, there are no additional requirements to any of the Stratix IV power supply inputs.
Page 405: Security Modes Available
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–67 Design Security At system power-up, the external memory device sends the encrypted configuration file to the Stratix IV device. Figure 10–29. Design Security (Note 1) Stratix IV Device...
Page 406: No Key Operation
10–68 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Design Security Enabling the tamper protection bit disables test mode in Stratix IV devices. This process is irreversible and prevents Altera from conducting carry-out failure analysis if test mode is disabled.
Page 407 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–69 Design Security Table 10–21 lists the configuration modes allowed in each of the security modes. Table 10–21. Allowed Configuration Modes for Various Security Modes (Note 1)
Page 408: Vccpd Pins
10–70 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Design Security Table 10–22. Document Revision History (Part 2 of 2) Date Version Changes Updated the “FPP Configuration Using a MAX II Device as an External Host”, “Fast Active ■...
Page 409 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 410: Error Detection Fundamentals
If the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. The error detection CRC feature uses the same concept. When Stratix IV devices are configured successfully and are in user mode, the error detection CRC feature ensures the integrity of the configuration data.
Page 411 This causes the CRC engine to start searching for the error bit location. Error detection in Stratix IV devices calculates CRC check bits for each frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a frame, it can detect all single-bit, double-bit, and three-bit errors.
Page 412 A JTAG instruction, EDERROR_INJECT, is provided to test the capability of the error detection block. This instruction is able to change the content of the 21-bit JTAG fault injection register that is used for error injection in Stratix IV devices, enabling the testing of the error detection block.
Page 413: Automated Single-Event Upset Detection
SEU. You can implement the error detection CRC feature with existing circuitry in Stratix IV devices, eliminating the need for external logic. The CRC_ERROR pin reports a soft error when the configuration CRAM data is corrupted. You must decide whether to reconfigure the device or to ignore the error.
Page 414: Error Detection Block
Chapter 11: SEU Mitigation in Stratix IV Devices Error Detection Block Error Detection Block You can enable the Stratix IV device error detection block in the Quartus II software (refer to “Software Support” on page 11–10). This block contains the logic necessary to calculate the 16-bit CRC signature for the configuration CRAM bits in the device.
Page 415: Error Detection Registers
Chapter 11: SEU Mitigation in Stratix IV Devices 11–7 Error Detection Block Error Detection Registers There is one set of 16-bit registers in the error detection circuitry that stores the computed CRC signature. A non-zero value on the syndrome register causes the CRC_ERROR pin to be set high.
Page 416: Error Detection Timing
11–8 Chapter 11: SEU Mitigation in Stratix IV Devices Error Detection Timing Table 11–4. Error Detection Registers (Part 2 of 2) Register Description This register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. It includes a clock enable that must be asserted prior JTAG Update Register to being sampled into the JTAG shift register.
Page 417 The error detection frequency reflects the frequency of the error detection process for a frame because the CRC calculation in the Stratix IV device is done on a per-frame basis. You must monitor the error message to avoid missing information in the error message register.
Page 418: Software Support
Quartus II software. To enable the error detection feature using CRC, follow these steps: 1. Open the Quartus II software and load a project using a Stratix IV device. 2. On the Assignments menu, click Settings. The Settings dialog box is shown.
Page 419: Recovering From Crc Errors
8. Click OK. Recovering From CRC Errors The system that the Stratix IV device resides in must control device reconfiguration. After detecting an error on the CRC_ERROR pin, strobing the nCONFIG signal low directs the system to perform the reconfiguration at a time when it is safe for the system to reconfigure the device.
Page 420 11–12 Chapter 11: SEU Mitigation in Stratix IV Devices Recovering From CRC Errors Document Revision History Table 11–8 lists the revision history for this chapter. Table 11–8. Document Revision History Date Version Changes Applied new template. ■ February 2011 Minor Text edits.
Page 421: Bst Architecture
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 422: Bst Operation Control
(1) For the F1932 package of EP4SGX290 and EP4SGX360 devices, the boundary-scan register length is 2970. Table 12–2 lists the IDCODE information for Stratix IV devices. Table 12–2. IDCODE Information for Stratix IV Devices (Part 1 of 2) IDCODE (32 Bits) Device...
Page 423 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices 12–3 BST Operation Control Table 12–2. IDCODE Information for Stratix IV Devices (Part 2 of 2) IDCODE (32 Bits) Device Manufacturer Identity Version (4 Bits) Part Number (16 Bits) (11 Bits)
Page 424: I/O Voltage Support In A Jtag Chain
BST Circuitry The IEEE Std. 1149.1 BST circuitry is enabled after device power-up. You can perform BST on Stratix IV devices before, during, and after configuration. Stratix IV devices support BYPASS, IDCODE, and SAMPLE JTAG instructions during configuration without interrupting configuration. To send all other JTAG instructions, you must interrupt configuration using the CONFIG_IO JTAG instruction.
Page 425 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices 12–5 BSDL Support Document Revision History Table 12–3 lists the revision history for this chapter. Table 12–3. Document Revision History Date Version Changes Applied new template. ■ February 2011 Minor text edits.
Page 426 12–6 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices BSDL Support Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 427: Overview
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 428: Stratix Iv Power Technology
The following sections describe Stratix IV programmable power technology. Programmable Power Technology Stratix IV devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation performed by the Quartus II software without user intervention. Setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies brought into the Stratix IV device.
Page 429: Stratix Iv External Power Supply Requirements
Stratix IV External Power Supply Requirements This section describes the different external power supplies required to power Stratix IV devices. You can supply some of the power supply pins with the same external power supply, provided they have the same voltage level.
Page 430: Temperature Sensing Diode
Temperature Sensing Diode Temperature Sensing Diode The Stratix IV TSD uses the characteristics of a PN junction diode to determine die temperature. Knowing the junction temperature is crucial for thermal management. Historically, junction temperature is calculated using ambient or case temperature, junction-to-ambient (ja) or junction to-case (jc) thermal resistance, and device power consumption.
Page 431 (mV) of difference, as seen at the external TSD pins. Switching the I/O near the TSD pins can affect the temperature reading. Altera recommends taking temperature readings during periods of inactivity in the device or use the internal TSD with built-in ADC circuitry.
Page 432 ■ Updated the “Temperature Sensing Diode” and “External Pin Connections” sections. ■ Updated Equation 13–1. ■ November 2009 Removed Table 13-2: Stratix IV External Power Supply Pins. ■ Minor text edits. ■ Updated the “External Pin Connections” section. ■ June 2009 Added an introductory paragraph to increase search ability.
Page 433: About This Handbook
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 434 Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.
Page 435 Reference Information ..............4–39 Chapter 5. Dynamic Reconfiguration in Stratix IV Devices Glossary of Terms .
Page 436 How to Contact Altera ........
Page 437 Contents Stratix IV Device Handbook September 2015 Altera Corporation Volume 2: Transceivers...
Page 438 Chapter Revision Dates The chapters in this document, Stratix IV Device Handbook Volume 2, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Transceiver Architecture in Stratix IV Devices...
Page 439 Chapter Revision Dates Stratix IV Device Handbook September 2015 Altera Corporation Volume 2: Transceivers...
Page 440 Chapter 1, Transceiver Architecture in Stratix IV Devices ■ Chapter 2, Transceiver Clocking in Stratix IV Devices ■ Chapter 3, Configuring Multiple Protocols and Data Rates in Stratix IV Devices Chapter 4, Reset Control and Power Down in Stratix IV Devices ■ ■...
Page 441 I–2 Section I: Transceiver Architecture Stratix IV Device Handbook September 2015 Altera Corporation Volume 2: Transceivers...
Page 442 © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 443 Chapter 1: Transceiver Architecture in Stratix IV Devices Overview Stratix IV GT devices are also part of Altera’s 40 nm Stratix IV device family and contain serial transceivers that support data rates between 600 Mbps and 11.3 Gbps. Stratix IV GT devices are targeted towards implementing 40 Gbps/100 Gbps transceiver links.
Page 444 1–3 Overview Figure 1–1 shows an example of the Stratix IV GX and GT transceiver architecture. Links to the corresponding transceiver architecture descriptions are listed below. This is an elementary diagram and does not represent an actual transceiver block. Figure 1–1. Example of a Transceiver Block...
Page 445 Stratix IV GX device member structured into full-duplex four- and six-channel groups called transceiver blocks. Table 1–3. Number of Transceiver Channels and Transceiver Block Locations in Stratix IV GX Devices (Part 1 of 2) Total Number of Device Member...
Page 446 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–5 Transceiver Channel Locations Table 1–3. Number of Transceiver Channels and Transceiver Block Locations in Stratix IV GX Devices (Part 2 of 2) Total Number of Device Member Transceiver Transceiver Channel Location...
Page 447 Figure 1–3 shows transceiver channel, PLL, and PCIe hard IP block locations in each Stratix IV GX device that has 24 or 36 transceiver channels (except for the EP4SGX530 device). Figure 1–3. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 24 or 36...
Page 448 Stratix IV GX devices that have 48 transceiver channels. Figure 1–4. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 48 Stratix IV GX Transceiver Channels and EP4SGX530 with 24, 36, and 48 Stratix IV GX Transceiver Channels...
Page 449 Stratix IV GT Device Offerings Table 1–4 lists the Stratix IV GT device offerings along with the number of transceiver channels available in each device. Table 1–4. Stratix IV GT Device Offerings and Transceiver Channels Available in Each Device Transceiver EP4S40G2F40 EP4S100G2F40...
Page 450 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–9 Transceiver Channel Locations Table 1–5. Transceiver Blocks in Stratix IV GT Devices Supporting Transceiver Channels up to 11.3 Gbps (Part 2 of 2) Total number of Transceiver Device Member Transceiver Channel Location...
Page 451 1–10 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Channel Locations Figure 1–5 shows the transceiver channel, PLL, and PCIe hard IP block locations for the EP4S40G2F40 Stratix IV GT devices. Figure 1–5. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S40G2F40...
Page 452 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–11 Transceiver Channel Locations Figure 1–6 shows the transceiver channel, PLL, and PCIe hard IP block locations for the EP4S40G5H40 Stratix IV GT devices. Figure 1–6. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S40G5H40...
Page 453 1–12 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Channel Locations Figure 1–7 shows the transceiver channel, PLL, and PCIe hard IP block locations in EP4S100G2F40 Stratix IV GT devices. Figure 1–7. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G2F40...
Page 454 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–13 Transceiver Channel Locations Figure 1–8 shows the transceiver channel, PLL, and PCIe hard IP block locations for the EP4S100G5H40 Stratix IV GT devices. Figure 1–8. Transceiver Channel, PLL, and Hard IP Block Locations in EP4S100G5H40...
Page 455 1–14 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Channel Locations Figure 1–9 shows the transceiver channel, PLL, and PCIe hard IP block locations for the EP4S100G3F45 and EP4S100G4F45 Stratix IV GT devices. Figure 1–9. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G3F45 and...
Page 456 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–15 Transceiver Channel Locations Figure 1–10 shows the transceiver channel, PLL, and PCIe hard IP block locations for the EP4S100G5F45 Stratix IV GT devices. Figure 1–10. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G5F45...
Page 457 1. Four full-duplex (transmitter and receiver) transceiver channels that support serial data rates from 600 Mbps to 8.5 Gbps in Stratix IV GX devices and 600 Mbps to 11.3 Gbps in Stratix IV GT devices. For more information, refer to “Transceiver...
Page 458 Four transceiver channels and two CMU channels are located in each transceiver block on the left and right sides of the device. Each Stratix IV GT device also has two 10G ATX PLLs that support data rates between 9.9 Gbps and 11.3 Gbps. Additionally, each Stratix IV GT device has two 6G ATX PLLs that support data rates between 600 Mbps and 6.5 Gbps, except the EP4S100G5F45 device that has four 6G ATX PLLs.
Page 459 1–18 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Each regular Stratix IV GT transceiver channel can be categorized into: ■ 8G transceiver channel—supports data rates between 600 Mbps and 8.5 Gbps 10G Transceiver Channel—supports data rates between 600 Mbps and 11.3 Gbps ■...
Page 460 ■ 8B/10B encoder Transmitter output buffer ■ The Stratix IV GX and GT transceiver provides the Enable low latency PCS mode ™ option in the ALTGX MegaWizard Plug-In Manager. If you select this option, the 8B/10B encoder in the datapath is disabled.
Page 461 1–20 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–7 lists the TX phase compensation FIFO modes. Table 1–7. TX Phase Compensation FIFO Modes Modes Description The FIFO is four words deep. Latency through the FIFO is two to three FPGA fabric parallel clock cycles (pending characterization).
Page 462 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–21 Transceiver Block Architecture TX Phase Compensation FIFO Status Signal An optional tx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation FIFO overflow or under-run condition. The...
Page 463 1–22 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture The byte serializer forwards the LSByte first, followed by the MSByte. The input data width to the byte serializer depends on the channel width option that you selected in the ALTGX MegaWizard Plug-In Manager.
Page 464 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–23 Transceiver Block Architecture 8B/10B Encoder The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. The 8B/10B encoder operates in two modes: single-width and double-width. Figure 1–17 shows the 8B/10B encoder in single-width and double-width mode.
Page 465 1–24 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–18 shows the conversion format. The LSB is transmitted first. Figure 1–18. 8B/10B Conversion Format control_code H G F E D C B A 8B/10B Conversion e d c b a...
Page 466 For example, depending on the current running disparity, the invalid code K24.1 (tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0 × 18C), which is equivalent to a D24.6+ (8'hD8 from the RD+ column). Altera recommends that you do not assert tx_ctrlenable for unsupported 8-bit characters.
Page 467 1–26 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture In double-width mode, the cascaded 8B/10B encoder generates two 10-bit code groups from two 8-bit data and their respective control code identifiers. Figure 1–21 shows the conversion format. The LSB shown in Figure 1–21...
Page 468 10'b0110001100 (0 × 18C), which is equivalent to a D24.6+ (8'hD8 from the RD+ column). An 8B/10B decoder can decode this and not assert a code error flag. Altera does not recommend sending invalid control words to the 8B/10B encoder. Reset Condition The tx_digitalreset signal resets the 8B/10B encoder.
Page 469 1–28 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture A high value on the tx_forcedisp port is the control signal to the disparity value of the output data. The disparity value (RD+ or RD-) is indicated by the value on the tx_dispval port.
Page 470 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–29 Transceiver Block Architecture K28.5 at the low byte position in time n + 4 should be encoded with a positive disparity. Because tx_forcedisp is high at time n + 4, the low signal level of tx_dispval is used to convert the lower byte K28.5 to be encoded as a positive...
Page 471 1–30 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–26 shows the transmitter polarity inversion feature in a single-width and double-width datapath configuration. Figure 1–26. Transmitter Polarity Inversion in Single-Width and Double-Width Mode Double-Width Configuration Single-Width Configuration...
Page 472 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–31 Transceiver Block Architecture Transmitter Bit Reversal Table 1–12 lists the transmission bit order with and without the transmitter bit reversal enabled. Table 1–12. Transmission Bit Order for the Bit Reversal Feature...
Page 473 1–32 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–28 shows the transmitter bit reversal feature in Basic double-width mode for a 20-bit wide datapath configuration. Figure 1–28. Transmitter Bit Reversal Operation in Basic Double-Width Mode...
Page 474 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–33 Transceiver Block Architecture Serializer The serializer converts the incoming low-speed parallel signal from the transceiver PCS to high-speed serial data and sends it to the transmitter buffer. The serializer supports an 8-bit or 10-bit serialization factor in single-width mode and a 16-bit or 20-bit serialization factor in double-width mode.
Page 475 (1) It is assumed that the input data to the serializer is 8 bits (channel width = 8 bits or 16 bits with the 8B/10B encoder disabled). Transmitter Output Buffer The Stratix IV GX and GT transmitter buffers are architecturally similar to each other. They both support programmable output differential voltage (V ), pre-emphasis, and on-chip termination (OCT) settings.
Page 476 (for more information, refer to “Calibration Blocks” on page 1–201), which compensates for temperature, voltage, and process changes. The Stratix IV GX and GT transmitter buffers in the transceiver are current mode drivers. Therefore, the resultant V is a function of the transmitter termination value.
Page 477 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Programmable Output Differential Voltage The Stratix IV GX and GT devices allow you to customize the differential output voltage to handle different trace lengths, various backplanes, and receiver requirements, as shown in Figure 1–32.
Page 478 ■ Serial RapidIO ■ XAUI ■ Stratix IV GT devices allow the high-speed links to be AC-coupled for the entire data rate range between 600 Mbps and 11.3 Gbps. September 2015 Altera Corporation Stratix IV Device Handbook Volume 2: Transceivers...
Page 479 Physical Medium TX Termination RX Termination The Stratix IV GX and GT transmitter can be DC-coupled to a Stratix IV GX and GT receiver for the entire operating data rate range of Stratix IV GX, from 600 Mbps to 8.5 Gbps.
Page 480 PCIe Electrical Idle The Stratix IV GX and GT transmitter output buffers support transmission of PCIe Electrical Idle (or individual transmitter tri-state). The tx_forceelecidle port puts the transmitter buffer in Electrical Idle mode. This port has a specific functionality in each power state.
Page 481 You can configure the receiver datapath using the ALTGX MegaWizard Plug-In Manager. Receiver Input Buffer The Stratix IV GX and GT receiver input buffers are architecturally similar to each other. They both support programmable common mode voltage (Rx V equalization, DC gain, and on-chip termination (OCT) settings.
Page 482 Table 1–17: (1) Programmable equalization settings are 1 to 16 dB for Stratix IV GX and GT devices; for example, rx_eqctrl = 4’h0 maps to 1 dB gain, rx_eqctrl = 4’h1 maps to 2 dB gain, and so on. The Stratix IV GX and GT receiver buffers support the following features: ■...
Page 483 OCT calibration support, refer to “Calibration Blocks” on page 1–201. Programmable V The Stratix IV GX and GT receiver buffers have on-chip biasing circuitry to establish the required V at the receiver input. It supports V settings of 0.82 V and 1.1 V that you can select in the ALTGX MegaWizard Plug-In Manager.
Page 484 RX Termination TX Termination Note to Figure 1–37: (1) The receiver termination and biasing can be on-chip or off-chip. The following protocols supported by Stratix IV GX and GT devices mandate AC-coupled links: ■ PCIe Gigabit Ethernet ■ Serial RapidIO ■...
Page 485 ■ (OIF) CEI PHY interface The following sections describe DC-coupling requirements for a high-speed link with a Stratix IV GX device used as the transmitter, receiver, or both. Specifically, the following link configurations are described: ■ Stratix IV GX Transmitter (PCML) to Stratix IV GX Receiver (PCML) ■...
Page 486 Stratix IV GX transmitter (PCML) to Stratix IV GX receiver (PCML) DC-coupled link. Table 1–19. Settings for a Stratix IV GX Transmitter (PCML) to Stratix IV GX Receiver (PCML) DC-Coupled Link Transmitter (Stratix IV GX) Settings...
Page 487 Stratix II GX to Stratix IV GX DC-coupled link. Table 1–20. Settings for a Stratix II GX to Stratix IV GX DC-Coupled Link Transmitter (Stratix II GX) Settings Receiver (Stratix IV GX) Settings...
Page 488 Stratix IV GX transmitter (PCML) to Stratix II GX receiver (PCML) DC-coupled link. Table 1–21. Settings for a Stratix IV GX to Stratix II GX DC-Coupled Link Transmitter (Stratix IV GX) Settings...
Page 489 1.1 V Notes to Table 1–22: (1) When DC-coupling an LVDS transmitter to the Stratix IV GX receiver, use RX V = 1.1 V and series resistance value RS to verify compliance with the LVDS specification. (2) Pending characterization. Link Coupling for Stratix IV GT Devices...
Page 490 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–49 Transceiver Block Architecture Table 1–23. Allowed DC-Coupling Scenarios for Stratix IV GT Devices (Part 2 of 2) From Data Rate Range Conditions (Transmitter I/O Standard) (Receiver I/O Standard) TX V = 0.7 V ■...
Page 491 Manually selecting optimal equalization settings is cumbersome under these changing system characteristics. The Adaptive Equalization feature solves this problem by enabling the Stratix IV device to continuously tune the receiver equalization settings based on the frequency content of the incoming signal and comparing it with internally generated reference signals.
Page 492 EyeQ The EyeQ hardware is available in Stratix IV GX and GT transceivers to analyze the receiver data recovery path, including receiver gain, clock jitter and noise level. You can use EyeQ to monitor the width of the incoming data eye and assess the quality of the incoming signal.
Page 493 1–52 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Normally, the receiver CDR samples the incoming signal at the center of the eye. When you enable the EyeQ hardware, it allows the CDR to sample across 32 different positions within one unit interval (UI) of a data eye.
Page 494 Transceiver Block Architecture Clock and Data Recovery Unit Each Stratix IV GX and GT receiver channel has an independent CDR unit to recover the clock from the incoming serial data stream. The high-speed and low-speed recovered clocks are used to clock the receiver PMA and PCS blocks.
Page 495 1–54 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture You can drive the receiver input reference clock with the following clock sources: ■ Dedicated REFCLK pins (refclk0 and refclk1) of the associated transceiver block Inter-transceiver block (ITB) clock lines from other transceiver blocks on the same ■...
Page 496 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–55 Transceiver Block Architecture PCIe Clock Switch Circuitry The feedback path from the CDR VCO to the PD has a /2 divider that is used in PCIe mode configured at Gen2 (5 Gbps) data rate for the dynamic switch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates.
Page 497 CDR is in LTD mode. If both signals are de- asserted, the CDR is in automatic lock mode. The Altera-recommended transceiver reset sequence varies depending on the CDR lock mode. For more information about reset sequence recommendations, refer to the...
Page 498 1–57 Transceiver Block Architecture Offset cancellation is executed automatically once each time a Stratix IV GX and GT device is powered on (after the device has finished programming and switches to user mode as indicated by CONFIG_DONE=1). The control logic for offset cancellation is integrated into the ALTGX_RECONFIG megafunction.
Page 499 1–58 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture After offset cancellation is complete, the divider settings are restored. Then the reconfiguration block sends and receives data to the ALTGX instance using the reconfig_togxb and reconfig_fromgxb buses. Connect the buses between the ALTGX_RECONFIG and ALTGX instances.
Page 500 Serial protocols such as PCIe, XAUI, Gigabit Ethernet, Serial RapidIO, and SONET/SDH, specify a standard word alignment pattern. For proprietary protocols, the Stratix IV GX and GT transceiver architecture allows you to select a custom word alignment pattern specific to your implementation.
Page 501 1–60 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–49 shows the word aligner operation in all supported configurations. Figure 1–49. Word Aligner in All Supported Configurations PMA-PCS Interface Width Single-Width Double-Width 10-Bit Wide 8-Bit Wide...
Page 502 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–61 Transceiver Block Architecture depending on whether the input signal rx_a1a2size is driven low or high, respectively. In Basic single-width mode, the word aligner looks for the 16-bit word alignment pattern programmed in the ALTGX MegaWizard Plug-In Manager. The word aligner aligns the 8-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal.
Page 503 1–62 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Bit-Slip Mode Word Aligner with 8-Bit PMA-PCS Interface Modes Basic single-width mode with 8-bit PMA-PCS interface width allows the word aligner to be configured in bit-slip mode. The word aligner operation is controlled by the input signal rx_bitslip in bit-slip mode.
Page 504 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–63 Transceiver Block Architecture Word Aligner in Single-Width Mode with 10-Bit PMA-PCS Interface Modes The following functional modes support the 10-bit PMA-PCS interface: ■ PCIe Gen1 and Gen2 Serial RapidIO ■ ■...
Page 505 1–64 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture In Basic single-width functional mode with a 10-bit PMA-PCS interface, you can configure the word aligner in automatic synchronization state machine mode by selecting the Use the built-in synchronization state machine option in the ALTGX MegaWizard Plug-In Manager.
Page 506 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–65 Transceiver Block Architecture Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the FPGA fabric to indicate the word aligner status. After receiving the first word alignment pattern after the rx_enapatternalign signal is asserted high, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle.
Page 507 1–66 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Bit-Slip Mode Word Aligner with 10-Bit PMA-PCS Interface Mode In some Basic single-width configurations with a 10-bit PMA-PCS interface, you can configure the word aligner in bit-slip mode by selecting the Use manual bit slipping mode option in the ALTGX MegaWizard Plug-In Manager.
Page 508 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–67 Transceiver Block Architecture Word aligner operation is controlled by the input signal rx_enapatternalign and is edge-sensitive to the rx_enapatternalign signal. A rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream.
Page 509 1–68 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Bit-Slip Mode Word Aligner with 16-Bit PMA-PCS Interface Modes In some Basic double-width configurations with 16-bit PMA-PCS interface, you can configure the word aligner in bit-slip mode by selecting the Use manual bit slipping mode option in the ALTGX MegaWizard Plug-In Manager.
Page 510 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–69 Transceiver Block Architecture Table 1–31 lists the word aligner options available in Basic single-width and double-width modes. Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes (Part 1 of 2)
Page 511 1–70 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes (Part 2 of 2) Word PMA-PCS Functional Word Alignment Alignment rx_enapatternalign rx_syncstatus rx_patterndetect Interface Mode Mode...
Page 512 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–71 Transceiver Block Architecture Programmable Run Length Violation Detection The programmable run length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal.
Page 513 1–72 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture The generic receiver polarity inversion feature is different from the PCIe 8B/10B polarity inversion feature. The generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner and is not available in PCIe mode.
Page 514 Transceiver Block Architecture Receiver Bit Reversal By default, the Stratix IV GX and GT receiver assumes a LSB-to-MSB transmission. If the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on the rx_dataout port. The receiver bit reversal feature is available to correct this situation.
Page 515 1–74 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–56 shows the receiver bit reversal feature in Basic double-width 20-bit wide datapath configurations. Figure 1–56. Receiver Bit Reversal in Double-Width Mode D[19] D[0] D[18] D[1] D[17]...
Page 516 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–75 Transceiver Block Architecture Receiver Byte Reversal in Basic Double-Width Modes The MSByte and LSByte of the input data to the transmitter may be erroneously swapped. The receiver byte reversal feature is available to correct this situation.
Page 517 1–76 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Deskew circuitry performs the deskew operation by the XAUI functional mode. Deskew circuitry consists of: A 16-word deep deskew FIFO in each of the four channels ■ Control logic in the CMU0 channel of the transceiver block that controls the deskew ■...
Page 518 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–77 Transceiver Block Architecture The deskew operation in XAUI functional mode is compliant to the PCS deskew state machine diagram specified in clause 48 of IEEE P802.3ae, as shown in Figure 1–59.
Page 519 1–78 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture The rate match FIFO consists of a 20-word deep FIFO and necessary logic that controls insertion and deletion of a skip character or ordered set, depending on the PPM difference.
Page 520 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–79 Transceiver Block Architecture The rate match FIFO inserts or deletes only one SKP symbol per SKP ordered set received. Rate match FIFO insertion and deletion events are communicated to the FPGA fabric on the pipestatus[2:0] port from each channel. The pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the /K28.5/ COM symbol...
Page 521 1–80 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–62 shows the rate match FIFO full condition in PCIe mode. The rate match FIFO becomes full after receiving data byte D4. Figure 1–62. Rate Match FIFO Full Condition in PCIe Mode...
Page 522 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–81 Transceiver Block Architecture Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||R|| column.
Page 523 1–82 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–65 shows an example of rate match insertion in the case where two ||R|| columns are required to be inserted. Figure 1–65. Rate Match Insertion in XAUI Mode...
Page 524 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–83 Transceiver Block Architecture The rate match FIFO can insert or delete as many /I2/ or /C2/ (first two bytes) as necessary to perform the rate match operation. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric.
Page 525 1–84 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Rate Match FIFO in Basic Single-Width Mode In Basic single-width mode, the rate match FIFO is capable of compensating for up to ±300 PPM (600 PPM total) difference between the upstream transmitter and the local receiver reference clock.
Page 526 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–85 Transceiver Block Architecture Figure 1–69 shows an example of rate match FIFO insertion in the case where three skip patterns are required to be inserted. In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
Page 527 1–86 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–71 shows the rate match FIFO empty condition in Basic single-width mode. The rate match FIFO becomes empty after reading out data byte D3. Figure 1–71. Rate Match FIFO Empty Condition in Basic Single-Width Mode...
Page 528 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–87 Transceiver Block Architecture The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip...
Page 529 1–88 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions. The rate match FIFO in Basic double-width mode automatically deletes the pair of data byte that causes the FIFO to go full and asserts the rx_rmfifofull flag synchronous to the subsequent pair of data bytes.
Page 530 The Stratix IV GX and GT receiver channel PCS datapaths implement the 8B/10B decoder after the rate matcher. In functional modes with rate matcher enabled, the 8B/10B decoder receives data from the rate matcher.
Page 531 1–90 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture The 8B/10B decoder operates in single-width mode in the following functional modes: PCIe ■ XAUI ■ ■ GIGE ■ Serial RapidIO ■ Basic single-width For PCIe, XAUI, GIGE, and Serial RapidIO functional modes, the ALTGX MegaWizard Plug-In Manager forces selection of the 8B/10B decoder in the receiver datapath.
Page 532 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–91 Transceiver Block Architecture Figure 1–78 shows the 8B/10B decoder decoding the received 10-bit /K28.5/ control code group into an 8-bit data code group (8'hBC) driven on the rx_dataout port. The rx_ctrldetect signal is asserted high synchronous with 8'hBC on the rx_dataout port, indicating that it is a control code group.
Page 533 1–92 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Control Code Group Detection The cascaded 8B/10B decoder indicates whether the decoded 16-bit code group is a data or control code group on the 2-bit rx_ctrldetect[1:0] port. The rx_ctrldetect[0] signal is driven high or low depending on whether decoded data on the rx_dataout[7:0] port (LSByte) is a control or data code group, respectively.
Page 534 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–93 Transceiver Block Architecture Byte Deserializer in Single-Width Mode In single-width mode, the byte deserializer receives 8-bit wide data from the 8B/10B decoder or 10-bit wide data from the word aligner (if the 8B/10B decoder is disabled) and deserializes it into 16-bit or 20-bit wide data at half the speed.
Page 535 (LSBytes) (LSBytes) Stratix IV GX and GT transceivers have an optional byte ordering block in the receiver datapath that you can use to restore proper byte ordering before forwarding the data to the FPGA fabric. The byte ordering block looks for the user-programmed byte ordering pattern in the byte-deserialized data.
Page 536 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–95 Transceiver Block Architecture Byte Ordering Block in Single-Width Modes Table 1–33 lists the single-width byte ordering block functional modes. Table 1–33. Single Width Functional Modes for the Byte Ordering Block Functional Modes...
Page 537 1–96 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Byte Ordering Block in Double-Width Modes Table 1–35 lists the double-width byte ordering block functional modes. Table 1–35. Double Width Functional Modes for the Byte Ordering Block Functional Modes...
Page 538 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–97 Transceiver Block Architecture The byte ordering block modes of operation in both single-width and double-width modes are: Word-alignment-based byte ordering ■ User-controlled byte ordering ■ Word-Alignment-Based Byte Ordering In word-alignment-based byte ordering, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data every time it sees a rising edge on the rx_syncstatus signal.
Page 539 1–98 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture User-Controlled Byte Ordering Unlike word-alignment-based byte ordering, user-controlled byte ordering provides control to the user logic to restore correct byte ordering at the receiver. When enabled, an rx_enabyteord port is available that you can use to trigger the byte ordering operation.
Page 540 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–99 Transceiver Block Architecture The receiver phase compensation FIFO write clock source varies with the receiver channel configuration. Table 1–37 lists the receiver phase compensation FIFO write clock source in different configurations.
Page 541 FIFO under-run or overflow condition as a probable cause of link errors. CMU Channel Architecture Stratix IV GX and GT devices contain two CMU channels—CMU0 and CMU1—within each transceiver block that you can configure as a transceiver channel or as a clock generation block.
Page 542 ×4 option in Basic mode). For more information, refer to “Functional Modes” on page 1–110. For Stratix IV GT devices, you can use the CMU PLL to generate transceiver clocks at data rates between 600 Mbps and 11.3 Gbps. CMU0 Channel The CMU0 channel, shown in Figure 1–88, contains the following blocks:...
Page 543 1–102 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture CMU0 PLL Figure 1–89 shows the CMU0 PLL. Figure 1–89. CMU0 PLL CMU0 PLL PLL Cascade Clock CMU0 Global Clock Line High-Speed CMU0 PLL Charge Pump Clock Input Reference...
Page 544 Power Down CMU0 PLL You can power down the CMU0 PLL by asserting the pll_powerdown signal. For more information, refer to the Reset Control and Power Down in Stratix IV Devices chapter. CMU0 Clock Divider The high-speed clock output from the CMU0 PLL is forwarded to two clock dividers: the CMU0 clock divider and the transmitter channel local clock divider.
Page 545 1–104 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture High-Speed Serial Clock Generation The /N divider receives the high-speed clock output from one of the CMU PLLs and produces a high-speed serial clock. Use this clock for bonded functional modes such as Basic ×4/×8, XAUI, and PCIe ×4/×8 configurations.
Page 546 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–105 Transceiver Block Architecture For more information about PCIe functional mode rate switching, refer to “PCIe Gen2 (5 Gbps) Support” on page 1–140. Figure 1–91. Rateswitch in PCIe Mode 250 MHz (Gen 1)
Page 547 Reset Control and Power Down in Stratix IV Devices chapter. Configuring CMU Channels as Transceiver Channels You can configure the two CMU channels in the transceiver block of Stratix IV GX and GT devices as full-duplex PMA-only channels to run between 600 Mbps and 6.5 Gbps.
Page 548 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–107 Transceiver Block Architecture Figure 1–93 shows the functional blocks that are enabled to support the transceiver channel functionality. Figure 1–93. Functional Blocks Enabled to Support Transceiver Channel Functionality From xN From xN...
Page 549 Table 1–39: (1) These indexes are for the Stratix IV GX and GT device with the maximum number of transceiver blocks. For exact information about how many of these pins are available for a specific device family, refer to the Overview for the Stratix IV Device Family chapter.
Page 550 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–109 Transceiver Block Architecture Clocks for the Transmitter Serializer When you configure the CMU channel as a transceiver channel, the clocks for the transmitter side is provided by one of these sources: ■...
Page 551 Table 1–41 lists the transceiver functional modes you can use to configure the Stratix IV GT devices using the ALTGX MegaWizard Plug-In Manager. Table 1–41. Functional Modes for the Stratix IV GT Devices (Part 1 of 2) Functional Mode Data Rate Refer To “Basic Single-Width Mode Configurations”...
Page 552 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–111 Transceiver Block Architecture Table 1–41. Functional Modes for the Stratix IV GT Devices (Part 2 of 2) Functional Mode Data Rate Refer To 2.5 Gbps ■ Serial RapidIO “Serial RapidIO Mode” on page 1–182 3.125 Gbps...
Page 553 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–43 lists the Stratix IV GT PCS-PMA interface widths and data rates supported in Basic single-width and double-width modes. Table 1–43. PCS-PMA Interface Widths and Data Rates Supported in Basic Single-Width and...
Page 554 Figure 1–95 shows Stratix IV GT transceiver configurations allowed in Basic single-width functional mode with an 8-bit PMA-PCS interface. Figure 1–94. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GX Devices Stratix IV GX Configurations...
Page 555 1–114 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–95. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GT Devices Stratix IV GT Configurations Protocol Basic Functional Single Double Deterministic...
Page 556 Figure 1–97 shows Stratix IV GT transceiver configurations allowed in Basic single-width functional mode with a 10-bit PMA-PCS interface. Figure 1–96. Transceiver Configurations in Basic Single-Width Mode with a 10-Bit PMA-PCS Interface for Stratix IV GX Devices Stratix IV GX Configurations...
Page 557 1–116 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–97. Transceiver Configurations in Basic Single-Width Mode with a 10-Bit PMA-PCS Interface for Stratix IV GT Devices Stratix IV GT Configurations Protocol Basic Functional Single Double SONET...
Page 558 Figure 1–99 shows Stratix IV GT transceiver configurations allowed in Basic double-width functional mode with a 16-bit PMA-PCS interface. Figure 1–98. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Stratix IV GX Devices Stratix IV GX Configurations...
Page 559 1–118 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–99. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Stratix IV GT Devices Stratix IV GT Configurations Protocol Basic Deterministic Functional Single Double...
Page 560 Figure 1–101 shows Stratix IV GT transceiver configurations allowed in Basic double-width functional mode with a 20-bit PMA-PCS interface. Figure 1–100. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit PMA-PCS Interface for Stratix IV GX Devices Stratix IV GX Configurations...
Page 561 1–120 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–101. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit PMA-PCS Interface for Stratix IV GT Devices Stratix IV GT Configurations Basic Protocol Deterministic Functional Single Double...
Page 562 Serial advanced technology attachment (SATA) and serial attached SCSI (SAS) are computer bus standards used in computers to transfer data between a mother board and mass storage devices. Stratix IV GX and GT devices offer options to implement a transceiver that satisfies SATA and SAS protocols. These options are: Transmitter in electrical idle mode ■...
Page 563 Transceiver Block Architecture Deterministic Latency Mode Stratix IV GX and GT devices have a deterministic latency option available for use in high-speed serial interfaces such as CPRI (Common Public Radio Interface) and Open Base Station Architecture Initiative Reference Point3 (OBSAI RP3). Both CPRI and OBSAI RP3 protocols place stringent requirements on the amount of latency variation that is permissible through a link implementing these protocols.
Page 564 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–123 Transceiver Block Architecture Receiver Bit Slipping The number of bits slipped in the receiver’s word aligner is given out on the rx_bitslipboundaryselectout[4:0] output port. The information on this output depends on your deserializer block width.
Page 565 1–124 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture In order to achieve deterministic latency through the transceiver, the reference clock to the CMU PLL must be the same as the low-speed parallel clock. For example, if you need a data rate of 1.2288 Gbps to be implemented for the CPRI protocol that places...
Page 566 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–125 Transceiver Block Architecture If the destination for high-speed serial data leaving the REC is the first RE, it is a single-hop connection. If serial data from the REC has to traverse through multiple REs before reaching the destination RE, it is a multi-hop connection.
Page 567 1–126 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Under the deterministic latency option, CPRI data rates can be implemented in single-width mode with 8/10-bit channel width and double-width mode with 16/20-bit channel width options only. Figure 1–105 shows the block diagram of the deterministic latency option.
Page 568 To implement a Version 2.0 PCIe-compliant PHY, you must configure the Stratix IV GX and GT transceivers in PCIe functional mode. Stratix IV GX and GT devices have built-in PCIe hard IP blocks that you can use to implement the PHY-MAC layer, data link layer, and transaction layer of the PCIe protocol stack.
Page 569 Transceiver Block Architecture PCIe Mode Configurations Stratix IV GX and GT transceivers support both Gen1 (2.5 Gbps) and Gen2 (5 Gbps) data rates in PCIe functional mode. When configured for the Gen2 (5 Gbps) data rate, the Stratix IV GX and GT transceivers allow dynamic switching between Gen2 (5 Gbps) and Gen1 (2.5 Gbps) signaling rates.
Page 570 Transceiver Block Architecture Figure 1–106 shows the Stratix IV GX and GT transceiver configurations allowed in PCIe functional mode. Figure 1–106. Stratix IV GX and GT Transceivers in PCIe Functional Mode Stratix IV GX and GT Configurations Protocol Basic Functional...
Page 571 Table 1–46 lists the transceiver datapath clock frequencies in PCIe functional mode configured using the ALTGX MegaWizard Plug-In Manager. Table 1–46. Stratix IV GX and GT Transceiver Datapath Clock Frequencies in PCIe Mode FPGA Fabric-Transceiver Parallel Recovered Interface Clock Frequency...
Page 572 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–131 Transceiver Block Architecture Transceiver datapath clocking varies between non-bonded (×1) and bonded (×4 and ×8) configurations in PCIe mode. For more information about transceiver datapath clocking in different PCIe configurations, refer to the Transceiver Clocking in Stratix IV Devices chapter.
Page 573 1–132 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–48. Supported Features in PCIe Mode (Part 2 of 2) 2.5 Gbps 5 Gbps Feature (Gen1) (Gen2) Receiver status encoding Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate —...
Page 574 The PCIe specification requires the receiver detect operation to be performed during the P1 power state. The PCIe interface block in Stratix IV GX and GT transceivers provide an input signal tx_detectrxloopback for the receiver detect operation. When the input signal...
Page 575 1–134 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–109 Figure 1–110 show the receiver detect operation where a receiver was successfully detected and where a receiver was not detected, respectively. Figure 1–109. Receiver Detect, Successfully Detected...
Page 576 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–135 Transceiver Block Architecture The PCIe protocol requires the first /K28.5/ code group of the compliance pattern to be encoded with negative current disparity. To satisfy this requirement, the PCIe interface block provides the input signal tx_forcedispcompliance. A high level on tx_forcedispcompliance forces the associated parallel transmitter data on the tx_datain port to transmit with negative current running disparity.
Page 577 LTSSM states and the four power states in the PCIe-compliant PHY. The PCIe interface in Stratix IV GX and GT transceivers provides an input port, powerdn[1:0], for each transceiver channel configured in PCIe mode.
Page 578 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–137 Transceiver Block Architecture The PCIe specification allows the PCIe interface to perform protocol functions; for example, receiver detect, loopback, and beacon transmission, in specified power states only. This requires the PHY-MAC layer to drive the tx_detectrxloopback and tx_forceelecidle signals appropriately in each power state to perform these functions.
Page 579 255 FTS (~4 us at Gen1 data rate and ~2 us at Gen2 data rate). If you have configured the Stratix IV GX and GT receiver CDR in Automatic Lock mode, the receiver cannot meet the PCIe specification of acquiring bit and byte synchronization within 4 s (Gen1 data rate) or 2 s (Gen2 data rate) due to the signal...
Page 580 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–139 Transceiver Block Architecture Table 1–52 lists electrical idle inference conditions specified in the PCIe Base Specification 2.0 and implemented in the Electrical Idle Inference module to infer electrical idle in various substates of the LTSSM state machine. For the Electrical Idle...
Page 581 When the Stratix IV GX and GT device is operating as a downstream device at PCIe Gen 2 data rates and if it goes into the Disable State, the Stratix IV GX and GT receiver must receive an Electrical Idle Exit condition in order to move out of the Disable state.
Page 582 Rate signal specified in the PCIe specification. The PHY-MAC layer can use the rateswitch signal to instruct the Stratix IV GX and GT device to operate at either Gen1 (2.5 Gbps) or Gen2 (5 Gbps) data rate, depending on the negotiated speed between the upstream and downstream ports.
Page 583 Gen2 (5 Gbps) signaling rates, both the transmitter high-speed serial and low-speed parallel clock and the CDR recovered clock must switch to support the instructed data rate. Stratix IV GX and GT transceivers have dedicated PCIe clock switch circuitry located in the following blocks: ■...
Page 584 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–143 Transceiver Block Architecture PCIe transmitter high-speed serial and low-speed parallel clock switch occurs: ■ In PCIe ×1 mode, the CMU_PLL clock switch occurs in the local clock divider in each transceiver channel.
Page 585 1–144 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCIe x1 Mode Figure 1–114 shows the PCIe rateswitch circuitry in PCIe ×1 mode configured at Gen2 (5 Gbps) data rate.
Page 586 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–145 Transceiver Block Architecture The PCIe clock switch circuitry in the local clock divider block performs the clock switch between 250 MHz and 500 MHz on the low-speed parallel clock when switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates. It indicates successful completion of clock switch on the pcie_gen2switchdone signal to the PCIe rateswitch controller.
Page 587 1–146 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCIe ×4 Mode Figure 1–116 shows the PCIe rateswitch circuitry in PCIe ×4 mode configured at Gen2 (5 Gbps) data rate.
Page 588 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–147 Transceiver Block Architecture Table 1–55. Transceiver Clock Frequencies Signaling Rates in PCIe ×4 Mode (Part 2 of 2) Gen1 (2.5 Gbps) to Gen2 (5 Gbps) Switch Gen2 (5 Gbps) to Gen1 (2.5 Gbps) Switch...
Page 589 1–148 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture collision of the phase compensation FIFO pointers, the PCIe rateswitch controller automatically disables and resets the phase compensation FIFO pointers of all bonded channels during clock switch. When the PCIe clock switch circuitry in the local clock divider indicates successful clock switch completion, the PCIe rateswitch controller releases the phase compensation FIFO pointer resets.
Page 590 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–149 Transceiver Block Architecture In PCIe ×8 mode configured at 5 Gbps data rate, when the PCIe rateswitch controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal...
Page 591 1–150 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–119 shows the low-speed parallel clock switch between Gen1 (250 MHz) and Gen2 (500 MHz) in response to the change in the logic level on the rateswitch signal.
Page 592 100 ms the link to become active The time taken by a PCIe port implemented using the Stratix IV GX and GT device to go from power up to link active state is described below: Power on reset (POR)—begins after power rails become stable. Typically takes ■...
Page 593 FPGA fabric to transfer to different polling compliance states using an external push button or user logic. If you use the Stratix IV GX and GT PCIe hard IP block, assert the test_in[6] port of the PCIe Compiler-generated wrapper file in your design. Asserting this port forces the LTSSM within the hard IP block to transition to these states.
Page 594 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–153 Transceiver Block Architecture XAUI Mode XAUI is an optional, self-managed interface that you can insert between the reconciliation sublayer and the PHY layer to transparently extend the physical reach of the XGMII.
Page 595 XGMII and also reduces the interface pin count. In Stratix IV GX and GT XAUI functional mode, the interface between the transceiver and FPGA fabric is 64 bits wide (four channels of 16 bits each) at single data rate.
Page 596 ||R|| Skip column /K28.0/K28.0/K28.0/K28.0/ ||A|| Align column /K28.3/K28.3/K28.3/K28.3/ Stratix IV GX and GT transceivers configured in XAUI mode provide the following protocol features: ■ XGMII-to-PCS code conversion at the transmitter ■ PCS-to-XGMII code conversion at the receiver 8B/10B encoding and decoding ■...
Page 597 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–123 shows the XAUI mode configuration supported in Stratix IV GX and GT devices. Figure 1–123. Stratix IV GX and GT XAUI Mode Configuration Stratix IV GX and GT Configurations...
Page 598 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–157 Transceiver Block Architecture XAUI Mode Datapath Figure 1–124 shows the ALTGX megafunction transceiver datapath when configured in XAUI mode. Figure 1–124. Transceiver Datapath in XAUI Mode Channel 3 Channel 2 Transmitter Channel PCS...
Page 599 Transceiver Block Architecture XGMII-To-PCS Code Conversion at the Transmitter In XAUI mode, the 8B/10B encoder in the Stratix IV GX and GT transmitter datapath is controlled by a transmitter state machine that maps various 8-bit XGMII codes to 10-bit PCS code groups. This state machine complies with the IEEE P802.3ae PCS...
Page 600 (1) The values in the XGMII TXD column are in hexadecimal. PCS-To-XGMII Code Conversion at the Receiver In XAUI mode, the 8B/10B decoder in the Stratix IV GX and GT receiver datapath is controlled by a XAUI receiver state machine that converts received PCS code groups into specific 8-bit XGMII codes.
Page 601 1–160 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Word Aligner The word aligner in XAUI functional mode is configured in automatic synchronization state machine mode. The Quartus II software automatically configures the synchronization state machine to indicate synchronization when the receiver receives four /K28.5/ comma code groups without intermediate invalid code...
Page 602 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–161 Transceiver Block Architecture Receiver synchronization is indicated on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that it has fallen out of synchronization. The receiver loses synchronization when it detects four invalid code groups separated by less than four valid code groups or when it is reset.
Page 603 1–162 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture After alignment of the first ||A|| column, if three additional aligned ||A|| columns are observed at the output of the deskew FIFOs of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
Page 604 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–163 Transceiver Block Architecture Rate Match FIFO In XAUI mode, the rate match FIFO is capable of compensating for up to ±100 PPM (200 PPM total) difference between the upstream transmitter and the local receiver reference clock.
Page 605 1–164 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–130 shows an example of rate match insertion in the case where two ||R|| columns are required to be inserted. Figure 1–130. Rate Match Insertion in XAUI Mode...
Page 606 Serialization and deserialization ■ Stratix IV GX and GT transceivers do not have built-in support for other PCS functions; for example, auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in a PLD logic array or external circuits.
Page 607 1–166 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–132 shows the GIGE mode configuration supported in Stratix IV GX devices. Figure 1–132. GIGE Mode for Stratix IV GX Devices Stratix IV GX Configurations Protocol Basic...
Page 608 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–167 Transceiver Block Architecture GIGE Mode Datapath Figure 1–133 shows the transceiver datapath when configured in GIGE functional mode. Figure 1–133. GIGE Mode Datapath Transmitter Channel PMA Transmitter Channel PCS FPGA TX Phase...
Page 609 1–168 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–63. GIGE Ordered Sets (Part 2 of 2) Number of Code Code Ordered Set Encoding Groups IDLE — Correcting /I1/, Preserving /I2/ /I1/ IDLE 1 /K28.5/D5.6 /I2/ IDLE 2 /K28.5/D16.2...
Page 610 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–169 Transceiver Block Architecture Reset Condition After de-assertion of tx_digitalreset, the GIGE transmitter automatically transmits three /K28.5/ comma code groups before transmitting user data on the tx_datain port. This could affect the synchronization state machine behavior at the receiver.
Page 611 1–170 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Table 1–64 lists the synchronization state machine parameters when configured in GIGE mode. Table 1–64. Synchronization State Machine Parameters in GIGE Functional Mode Synchronization State Machine Parameters Setting Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve synchronization...
Page 612 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–171 Transceiver Block Architecture Rate Match FIFO In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM (200 PPM total) difference between the upstream transmitter and the local receiver reference clock.
Page 613 ■ A2 = 00101000 or 8'h28 You can employ Stratix IV GX and GT transceivers as physical layer devices in a SONET/SDH system. These transceivers provide support for SONET/SDH protocol-specific functions and electrical features; for example, alignment to A1A2 or A1A1A2A2 pattern.
Page 614 1–173 Transceiver Block Architecture Stratix IV transceivers are designed to support the following three SONET/SDH sub-protocols: OC-12 at 622 Mbps with 8-bit channel width (not supported in Stratix IV GT ■ devices) OC-48 at 2488.32 Mbps with 16-bit channel width ■...
Page 615 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Figure 1–140 shows SONET/SDH mode configurations supported in Stratix IV GX and GT devices. Figure 1–140. SONET/SDH Mode Configurations in Stratix IV GX and GT Devices Stratix IV GX and GT Configurations Protocol Basic Deterministic...
Page 616 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–175 Transceiver Block Architecture SONET/SDH OC-12 Datapath Figure 1–141 shows the transceiver datapath when configured in SONET/SDH OC-12 mode. Figure 1–141. SONET/SDH OC-12 Datapath Transmitter Channel PCS FPGA Transmitter Channel PMA Fabric...
Page 617 1–176 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture SONET/SDH OC-96 Datapath Figure 1–143 shows the transceiver datapath when configured in SONET/SDH OC-96 mode. Figure 1–143. SONET/SDH OC-96 Datapath Transmitter Channel PCS Transmitter Channel PMA FPGA Fabric...
Page 618 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–177 Transceiver Block Architecture You can configure the word aligner to flip the alignment pattern bits programmed in the MegaWizard Plug-In Manager and compare them with the incoming data for alignment. This feature offers flexibility to the SONET backplane system for either a MSB-to-LSB or LSB-to-MSB data transfer.
Page 619 SMPTE 424M standard—more popularly known as the third-generation (3G) SDI, is defined to carry video data at either 2970 Mbps or 2967 Mbps You can configure Stratix IV GX and GT transceivers in HD-SDI or 3G-SDI configuration using the ALTGX MegaWizard Plug-In Manager.
Page 620 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–179 Transceiver Block Architecture Figure 1–145 shows SDI mode configurations supported in Stratix IV GX and GT devices. Figure 1–145. SDI Mode Stratix IV GX and GT Configurations Protocol Basic Deterministic Single...
Page 621 Receiver Word Alignment and Framing In SDI systems, the word aligner in the receiver datapath is not useful because word alignment and framing happens after de-scrambling. Altera recommends driving the ALTGX megafunction rx_bitslip signal low to avoid having the word aligner insert bits in the received data stream.
Page 622 1–181 Transceiver Block Architecture (OIF) CEI PHY Interface Mode Stratix IV GX and GT transceivers support a data rate between 4.976 Gbps and 6.375 Gbps in (OIF) CEI PHY interface mode. Figure 1–147 shows (OIF) CEI PHY interface mode configurations supported in Stratix IV GX and GT devices.
Page 623: Peripheral Devices
1–182 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture (OIF) CEI PHY Interface Mode Datapath Figure 1–148 shows the ALTGX megafunction transceiver datapath when configured in (OIF) CEI PHY interface mode. Figure 1–148. (OIF) CEI PHY Interface Mode Datapath...
Page 624 ■ ■ Serialization/deserialization Stratix IV GX and GT transceivers do not have built-in support for other PCS functions; for example, pseudo-random idle sequence generation and lane alignment in 4× mode. Depending on your system requirements, you must implement these functions in the logic array or external circuits.
Page 625 1–184 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Synchronization State Machine In Serial RapidIO mode, the ALTGX MegaWizard Plug-In Manager defaults the word alignment pattern to K28.5. The word aligner has a synchronization state machine that handles the receiver lane synchronization.
Page 626 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–185 Transceiver Block Architecture Figure 1–151 shows a conceptual view of the synchronization state machine implemented in Serial RapidIO functional mode. Figure 1–151. Synchronization State Machine in Serial RapidIO Mode Loss of Sync...
Page 627 1–186 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Depending on your implementation, you can select two 20-bit rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is the rate match pattern1 and What is the rate match pattern2 fields. Each of the two programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit control pattern.
Page 628 1–84. Basic (PMA Direct) Functional Mode In Basic (PMA Direct) functional mode, the Stratix IV GX and GT transceiver datapath contains only PMA blocks. Parallel data is transferred directly between the FPGA fabric and the serializer/deserializer inside the transmitter/receiver PMA. Because all PCS blocks are bypassed in Basic (PMA Direct) mode, you must implement the required PCS logic in the FPGA fabric.
Page 629 Stratix IV GX and GT transceiver configured in Basic (PMA Direct) functional mode. The grayed out blocks indicate areas that are not active in this mode. Figure 1–154. Stratix IV GX and GT Transceiver Configured in Basic (PMA Direct) Mode Transmitter Channel PCS Transmitter Channel...
Page 630 Transceiver Block Architecture Table 1–68 lists the Stratix IV GX and GT PLD-PMA interface widths and data rates supported in Basic (PMA Direct) ×1/×N single-width and double-width modes. Table 1–68. FPGA Fabric-PMA Interface Widths and Data Rates Supported in Basic (PMA Direct) ×1/×N Single-Width and...
Page 631 AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode. Loopback Modes Stratix IV GX and GT devices provide various loopback options that allow you to verify how different functional blocks work in the transceiver channel. The available loopback options are: ■...
Page 632 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–191 Transceiver Block Architecture When moving into or out of serial loopback, you must assert rx_digitalreset for a minimum of two parallel clock cycles. Figure 1–155. Serial Loopback Datapath Transmitter Channel PMA...
Page 633 1–192 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture The parallel loopback mode is available only with a built-in 16-bit incremental pattern generator and verifier. The channel width is fixed to 16 bits in this mode. Also in this mode, the incremental pattern 00-FF is looped back to the receiver channel at the PCS functional block boundary before the PMA and is sent to the tx_dataout port.
Page 634 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–193 Transceiver Block Architecture Reverse Serial Loopback The Reverse Serial Loopback can be set by selecting the radial button under the Loopback tab in the ALTGX MegaWizard. In reverse serial loopback mode, the data is received through the rx_datain port, retimed through the receiver CDR and sent out to the tx_dataout port.
Page 635 1–194 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Block Architecture Reverse Serial Pre-CDR Loopback The reverse serial pre-CDR loopback is available as a subprotocol under Basic functional mode. In reverse serial pre-CDR loopback, the data received through the rx_datain port is looped back to the tx_dataout port before the receiver CDR.
Page 636 6G ATX PLL Block Stratix IV GX can have either two (one on each side of the device) or four (two on each side of the device) 6G ATX PLLs, depending on the specific devices. For data rates supported by 6G ATX PLLs, refer to the...
Page 637 Auxiliary Transmit (ATX) PLL Block 10G ATX PLL Block Each Stratix IV GT device has two 10G ATX PLL blocks, one located on each side of the device. The 10G ATX PLLs provide low-jitter transceiver clocks to implement 40G/100G Ethernet and SFI-S links specified by IEEE802.3ba and OIF specifications.
Page 638 ATX PLL blocks in three transceiver block device families (for 230K and 530K devices and all other devices). Figure 1–161. Location of ATX PLL Blocks with a Six Transceiver Block Stratix IV GX Device (Three on Each side)
Page 639 Figure 1–164 show the locations of the 6G and 10G ATX PLLs in each Stratix IV GT device. Figure 1–163. Location of Transceiver Channel and PLL in Stratix IV GT Devices (EP4S40G2F40, EP4S40G5H40, EP4S100G2F40 and EP4S100G5H40) Transceiver Block GXBL2 Transceiver Block GXBR2...
Page 640 1–199 Auxiliary Transmit (ATX) PLL Block For the 10G ATX PLL, Stratix IV GT devices only allow driving the reference clock source from one of the dedicated reflck pins on the same side of the device. For improved jitter performance, Altera strongly recommends using the REFCLK pins of the transceiver block located immediately below the 10G ATX PLL block to drive the input reference clock.
Page 641 1–200 Chapter 1: Transceiver Architecture in Stratix IV Devices Auxiliary Transmit (ATX) PLL Block ATX Clock Divider The ATX clock divider divides the ATX PLL high-speed clock and provides high-speed serial and low-speed parallel clock for bonded functional modes such as PCIe (×4 and ×8), Basic ×4 and ×8, and PMA-Direct mode with ×N configuration.
Page 642 1–70: (1) Using the L dividers available in ATX PLLs. (2) For improved jitter performance, Altera strongly recommends using the refclk pins of the transceiver block located immediately below the 10G ATX PLL block to drive the input reference clock.
Page 643 Stratix IV GX 230K and 530K devices that have three transceiver blocks each on the left and right side and one ATX PLL block on each side. Figure 1–168. Calibration Block Locations in Stratix IV GX 230K and 530K Devices with Three Transceiver Blocks (on Each Side) Ω...
Page 644 ATX PLL blocks on each side. Figure 1–169. Calibration Block Locations in Stratix IV GX Devices Other than 230K and 530K with Three Transceiver Blocks (on Each Side) Ω...
Page 645 Stratix IV GX devices that have four transceiver blocks each on the left and right side and two ATX PLL blocks on each side. Figure 1–170. Calibration Block Locations in Stratix IV GX Devices with Four Transceiver Blocks (on Each Side) Ω...
Page 646 You must connect a separate 2 k (tolerance max ± 1%) external resistor on each RREF pin in the Stratix IV GX and GT device to ground. To ensure proper operation of the calibration block, the RREF resistor connection in the board must be free from external noise.
Page 647 1–206 Chapter 1: Transceiver Architecture in Stratix IV Devices Calibration Blocks Figure 1–172 shows the required inputs to the calibration block. Figure 1–172. Input Signals to the Calibration Blocks Calibration Block RREF pin Internal cal_blk_clk Reference Voltage cal_blk_powerdown (1) Generator...
Page 648 This section describes Built-In Self Test (BIST) modes. BIST Mode Pattern Generators and Verifiers Each transceiver channel in the Stratix IV GX and GT devices contain a different BIST pattern generator and verifier. Using these BIST patterns, you can verify the functionality of the functional blocks in the transceiver channel without requiring user logic.
Page 649 1–208 Chapter 1: Transceiver Architecture in Stratix IV Devices Built-In Self Test Modes Different PRBS patterns are available as a subprotocol under Basic functional mode for single-width and double-width mode, as shown in the following sections. You can enable the serial loopback option in Basic PRBS mode to loop the generated pattern to the receiver channel.
Page 650 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–209 Built-In Self Test Modes Table 1–71. Available PRBS, High Frequency, and Low Frequency Patterns in Single-Width Mode Maximum Maximum Word Data Rate Data Rate Channel Alignment Channel Word With with Patterns...
Page 651 Table 1–79 list a brief description of the ALTGX megafunction ports. Table 1–73 lists the ALTGX megafunction transmitter ports. Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 1 of 3) Input/ Port Name Clock Domain Description...
Page 652 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–211 Transceiver Port Lists Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 2 of 3) Input/ Port Name Clock Domain Description Scope Output 8B/10B Encoder 8B/10B encoder /Kx.y/ or /Dx.y/ control.
Page 653 1–212 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Port Lists Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 3 of 3) Input/ Port Name Clock Domain Description Scope Output Transmitter polarity inversion control. This...
Page 654 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–213 Transceiver Port Lists Table 1–74 lists the ALTGX megafunction receiver ports. Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 1 of 7) Input/ Port Name Clock Domain Description...
Page 655 1–214 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 2 of 7) Input/ Port Name Clock Domain Description Scope Output Generic receiver polarity inversion control.
Page 656 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–215 Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 3 of 7) Input/ Port Name Clock Domain Description Scope Output Deskew FIFO XAUI deskew FIFO channel aligned indicator.
Page 657 1–216 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 4 of 7) Input/ Port Name Clock Domain Description Scope Output 8B/10B Decoder Receiver control code indicator.
Page 658 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–217 Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 5 of 7) Input/ Port Name Clock Domain Description Scope Output 8B/10B running disparity indicator.
Page 659 1–218 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 6 of 7) Input/ Port Name Clock Domain Description Scope Output Optional read clock port for the receiver phase compensation FIFO.
Page 660 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–219 Transceiver Port Lists Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 7 of 7) Input/ Port Name Clock Domain Description Scope Output Receiver CDR lock-to-reference mode control signal.
Page 661 (with rate match FIFO enabled) into the FPGA fabric. Table 1–76 lists the ALTGX megafunction dynamic reconfiguration ports. Table 1–76. Stratix IV GX and GT ALTGX Megafunction Ports: Dynamic Reconfiguration (Part 1 of 2) Input/ Port Name Clock Domain...
Page 662 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–221 Transceiver Port Lists Table 1–76. Stratix IV GX and GT ALTGX Megafunction Ports: Dynamic Reconfiguration (Part 2 of 2) Input/ Port Name Clock Domain Description Scope Output Asynchronous reconfig_togxb Input From the dynamic reconfiguration controller.
Page 663 1–222 Chapter 1: Transceiver Architecture in Stratix IV Devices Transceiver Port Lists Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 2 of 4) Input/ Port Name Clock Domain Description Scope Output Transmitter differential output voltage level control.
Page 664 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–223 Transceiver Port Lists Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 3 of 4) Input/ Port Name Clock Domain Description Scope Output Receiver detect or PCIe loopback control.
Page 665 Table 1–78 lists the ALTGX megafunction reset and power down ports. Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 1 of 2) Input/ Port Name Clock Domain...
Page 666 Chapter 1: Transceiver Architecture in Stratix IV Devices 1–225 Reference Information Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 2 of 2) Input/ Port Name Clock Domain Description Scope Output Asynchronous Receiver PMA reset.
Page 667 1–226 Chapter 1: Transceiver Architecture in Stratix IV Devices Reference Information Table 1–80. Reference Information (Part 2 of 3) Terms Used in this Chapter Useful Reference Points CPRI and OBSAI page 1–124 Deserializer page 1–58 Deskew FIFO page 1–75 Deterministic Latency Mode page 1–122...
Page 668 Updated the “Overview”, “Transceiver Block Architecture”, “DC-Coupled Links”, “Link ■ Coupling for Stratix IV GX and GT Devices”, “Configuring CMU Channels for Clock Generation”, “Configuring CMU Channels as Transceiver Channels”, “Offset Cancellation in the Receiver Buffer and Receiver CDR”, “Modes of Operation of the AEQ”, “Word-Alignment-Based Byte Ordering”, “SATA and SAS Options”, “GIGE Mode”.
Page 669 1–228 Chapter 1: Transceiver Architecture in Stratix IV Devices Reference Information Table 1–81. Document Revision History (Part 2 of 2) Date Version Changes Added two references to the beginning of the chapter. ■ Updated the “Configuring CMU Channels for Clock Generation” section.
Page 670 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 671 CDR that uses the input reference clock as a training clock when it is in LTR mode. Each Stratix IV device also has ATX PLLs that you can use in addition to the CMU PLLs to generate the high-speed serial transceiver clock. The ATX PLLs also need an input reference clock for operation.
Page 672 (2) For more information, refer to “Inter-Transceiver Block (ITB) Clock Lines” on page 2–8. (3) For better jitter performance, Altera strongly recommends using the refclk0 and refclk1 pins of the transceiver block located immediately below the ATX PLL. (4) Lowest number indicates best jitter performance.
Page 673 2–4 Chapter 2: Transceiver Clocking in Stratix IV Devices Input Reference Clocking Figure 2–2 shows the input reference clock sources for CMU PLLs and receiver CDRs within a transceiver block. One global clock line is available for each CMU PLL and receiver CDR in a transceiver block.
Page 674 Figure 2–3 also shows the ITB clock lines on the right side of the device. The number of ITB clock lines available in any Stratix IV GX device is equal to the number of refclk pins available in that device.
Page 675 Figure 2–4 also shows the ITB clock lines on the right side of the EP4S100G5F45 device. The number of ITB clock lines available in any Stratix IV GT device is equal to the number of refclk pins available in that device.
Page 676 The refclk pins provide the cleanest input reference clock path to the CMU/ATX PLLs when compared with other input reference clock sources. Altera recommends using the refclk pins to drive the CMU PLL input reference clock for improved transmitter output jitter performance.
Page 677 Dedicated CLK Input Pins on the FPGA Global Clock Network Stratix IV devices provide up to eight differential clock input pins located in non-transceiver I/O banks that you can use to provide up to eight input reference ®...
Page 678 PLL_L3, and PLL_L4) in the FPGA fabric to the PLL cascade network located on the left side of the device. Stratix IV devices also provide a dedicated clock path from the right PLLs (PLL_R1, PLL_R2, PLL_R3, and PLL_R4) in the FPGA fabric to the PLL cascade network located on the right side of the device.
Page 679 FPGA Fabric PLLs-Transceiver PLLs Cascading Dedicated Left and Right PLL Cascade Network Stratix IV devices have a dedicated PLL cascade network on the left and right side of the device that connects to the input reference clock selection multiplexer of the CMU PLLs, 6G ATX PLLs, and receiver CDRs on the left and right side of the device, respectively.
Page 680 2–11 FPGA Fabric PLLs-Transceiver PLLs Cascading FPGA Fabric PLLs-Transceiver PLLs Cascading in the 780-Pin Package Stratix IV GX devices in 780-pin packages do not support FPGA fabric PLLs-transceiver PLLs cascading. FPGA Fabric PLLs-Transceiver PLLs Cascading in the 1152-Pin Package Figure 2–6...
Page 681 10G ATX PLLs. For the EP4S40G2KF40, EP4S40G5KF40, EP4S100G2KF40, and EP4S100G5KF40 devices, FPGA fabric PLLs-Transceiver PLLs cascading for the 6G ATX PLLs and CMU PLLs is the same as the Stratix IV GX devices in the 1517-pin package.
Page 682 10G ATX PLLs. For the EP4S100G3NF45, EP4S100G4N45, and EP4S100G5NF45 devices, FPGA fabric PLLs-Transceiver PLLs cascading for the 6G ATX PLLs and CMU PLLs is the same as the Stratix IV GX devices in the 1932-pin package. Figure 2–8. FPGA Fabric PLLs-Transceiver PLLs Cascading Options Allowed in the 1932-Pin Package Device...
Page 683 2–14 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric PLLs-Transceiver PLLs Cascading FPGA Fabric PLLs-Transceiver PLLs Cascading Rules You can only cascade the left PLLs (PLL_L1, PLL_L2, PLL_L3, and PLL_L4) to the transceiver blocks located on the left side of the device. Similarly, you can only cascade the right PLLs (PLL_R1, PLL_R2, PLL_R3, and PLL_R4) to the transceiver blocks located on the right side of the device.
Page 684 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–15 FPGA Fabric PLLs-Transceiver PLLs Cascading Figure 2–9 shows that this FPGA fabric-Transceiver PLL cascading configuration is illegal due to crossover (shown in RED) of the cascade clock paths on the PLL cascade network.
Page 685 2–16 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric PLLs-Transceiver PLLs Cascading Case 2: use PLL_R1 to provide the input reference clock to the receiver CDRs in channel 2 and channel 3 (shown in BLUE) and use PLL_R4 to provide the input reference clock to the CMU0 PLL (shown in GREEN) in transceiver block GXBR1.
Page 686 CDRs. In such designs, you must use the 6G ATX PLLs to generate the high-speed serial and low-speed parallel transceiver clocks provided that the configured data rate is supported by the 6G ATX PLLs. Additionally, Altera recommends providing the input reference clock to the 6G ATX PLL using the left or right PLL cascade clock line because none of the refclk pins are available.
Page 687 2–18 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric PLLs-Transceiver PLLs Cascading Figure 2–12 shows 24 channels on the right side of the EP4SGX530NF45 device configured in Basic (PMA Direct) ×N mode running at 6.5 Gbps with a 20-bit FPGA fabric-PMA interface width.
Page 688 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–19 FPGA Fabric PLLs-Transceiver PLLs Cascading Figure 2–12. Input Reference Clocking Using Left and Right, Left, or Right PLL in VCO Bypass Mode xN_Bottom (1) PLL Cascade Clock Line Transceiver Block GXBR 3...
Page 689 Quartus II software. For more information about manually picking and placing CMU and ATX PLLs, refer AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices. Transmitter Channel Datapath Clocking...
Page 690 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–21 Transceiver Channel Datapath Clocking Transmitter Channel-to-Channel Skew Optimization for Modes Other than Basic (PMA Direct) Mode High-speed serial clock and low-speed parallel clock skew between channels and unequal latency in the transmitter phase compensation FIFO contribute to transmitter channel-to-channel skew.
Page 691 Figure 2–13 shows the transceiver clock distribution in ×1, ×4, ×8, and ×N bonded modes. Figure 2–13. Transceiver Clock Distribution in the Stratix IV GT EP4S100G5F45 and Stratix IV GX EP4SGX530KF40 Devices Transceiver Block GXBR3 CMU1 GXBR3...
Page 692 Bonded Transmitter channels configured in modes other than Basic (PMA Direct) mode use both the transmitter channel PCS and PMA blocks. As a result, Stratix IV devices allow placing these transmitter channels only in the four regular channels of a transceiver block.
Page 693 2–24 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking The transmitter channel datapath clocking in modes other than Basic (PMA Direct) mode depends on whether the transmitter channel is configured in non-bonded or bonded mode. Non-Bonded Channel Configurations...
Page 694 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–25 Transceiver Channel Datapath Clocking Figure 2–15 shows transmitter channel datapath clocking in non-bonded channel configurations when clocked using the CMU PLLs. Figure 2–15. Transmitter Datapath Clocking in a Non-Bonded Configuration Clocked by CMU PLLs...
Page 695 2–26 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking In non-bonded channel configurations clocked by the CMU PLL, each channel can derive its clock independently from either CMU0 PLL or CMU1 PLL within the same transceiver block. The CMU PLL synthesizes the input reference clock to generate a clock that is distributed to the local clock divider block in each channel using the ×1...
Page 696 FIFOs of all bonded channels also share common read and write pointers and enable signals generated in the CCU. Stratix IV devices support ×4 PCS and PMA channel bonding that allows bonding of four channels within the same transceiver block. Stratix IV devices also support ×8 channel bonding that allows bonding of eight PCS and PMA channels across two transceiver blocks on the same side of the device.
Page 697 2–28 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–16 shows the transmitter channel datapath clocking in ×4 channel bonding configurations when clocked using the CMU0 channel. Figure 2–16. Transmitter Datapath Clocking in x4 Bonded Configurations...
Page 698 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–29 Transceiver Channel Datapath Clocking The transceiver clocks are distributed to the four bonded channels on the ×4 high-speed serial and ×4 low-speed parallel clock lines. The serializer in the transmitter channel PMA of the four bonded channels uses the same low-speed parallel clock and high-speed serial clock from CMU0 Channel for their parallel-in-serial-out operation.
Page 699 To compensate for this difference in clock routing delays between the ×4 and the ×N clock lines, the Stratix IV transceivers introduce a fixed amount of delay in the ×4 clock lines of the transceiver block whose CMU0 channel generates the transceiver clocks in Basic ×8 bonded channel...
Page 700 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–31 Transceiver Channel Datapath Clocking Figure 2–17 shows the transmitter datapath clocking in PCIe ×8 channel bonding configurations when clocked using the CMU channel in the master transceiver block. Figure 2–17. Transmitter Datapath Clocking in x8 Bonded Configuration...
Page 701 2–32 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–18 shows one PCIe ×8 link in two transceiver block devices and two PCIe ×8 links in four transceiver block devices. Figure 2–18. One PCIe x8 Link in Two Transceiver Block Devices and Two PCIe x8 Links in Four Transceiver Block...
Page 702 Figure 2–19: (1) Stratix IV devices with six transceiver blocks allow a maximum of two PCIe ×8 links occupying four transceiver blocks. You can configure the other two transceiver blocks to implement other functional modes. (2) You can use a ×4 PCIe configuration in either a master or slave block.
Page 703 2–34 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–20 shows four PCIe ×8 links in eight transceiver block devices. Figure 2–20. Four PCIe ×8 Links in Eight Transceiver Block Devices EP4SGX530NF45 Transceiver Block Transceiver Block...
Page 704 (1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock. Stratix IV devices do not allow the 6G ATX PLL to generate transceiver clocks in non-bonded Basic (PMA Direct) mode. The transmitter clock for channels configured in non-bonded Basic (PMA Direct) mode must be generated by one of the CMU PLLs in the transceiver block containing the channels.
Page 705 PCS logic in the FPGA fabric. Stratix IV devices allow bonding all regular channels and CMU channels on one side of the device in Basic (PMA Direct) ×N mode. For example, devices such as EP4SGX530NF45 or EP4S100G5F45 allow bonding of up to 24 channels placed in four transceiver blocks on each side of the device.
Page 706 17 channels configured in Basic (PMA Direct) ×N mode and located across three transceiver blocks on the right side of the Stratix IV device. Each of the two transceiver blocks, GXBR0 and GXBR2, contain six of the 17 ×N bonded channels located in four regular channels and two CMU channels.
Page 707 To compensate for this difference in clock routing delays between the ×4 and the ×N clock lines, the Stratix IV transceivers introduce a fixed amount of delay in the ×4 clock lines of the transceiver block whose CMU0 channel generates the transceiver clocks.
Page 708 PCS logic in each channel. For more information about transceiver reset and power down signals, refer to the Reset Control and Power Down in Stratix IV Devices chapter. In non-bonded channel configurations, receiver channel datapath clocking has two scenarios: “Non-Bonded Receiver Clocking Without Rate Matcher”...
Page 709 2–40 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–23 shows receiver datapath clocking in non-bonded channel configurations without rate matcher. Figure 2–23. Receiver Datapath Clocking in Non-Bonded Configurations Without Rate Matcher Channel 3 Receiver Channel PCS...
Page 710 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–41 Transceiver Channel Datapath Clocking Depending on whether you use the byte deserializer or not, the parallel recovered clock (when you do not use the byte deserializer) or a divide-by-two version of the parallel recovered clock (when you use the byte deserializer) clocks the write port of the receiver phase compensation FIFO.
Page 711 2–42 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–24 shows the receiver datapath clocking in non-bonded channel configurations with rate matcher. Figure 2–24. Receiver Datapath Clocking in Non-Bonded Configurations with Rate Matcher Channel 3...
Page 712 156.25 Bonded Channel Configurations The Stratix IV device supports ×4 channel bonding that allows bonding of four channels within the same transceiver block. It also supports ×8 channel bonding that allows bonding of eight channels across two transceiver blocks on the same side of the device.
Page 713 2–44 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking x4 Bonded Channel Configuration with Deskew FIFO XAUI functional mode has ×4 bonded channel configuration with deskew FIFO. Figure 2–25 shows the receiver datapath clocking in ×4 channel bonding configurations with deskew FIFO.
Page 714 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–45 Transceiver Channel Datapath Clocking The parallel recovered clock from the receiver PMA in each channel clocks the word aligner in that channel. The parallel recovered clock from Channel 0 clocks the deskew FIFO and the write port of the rate match FIFO in all four bonded channels.
Page 715 2–46 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking x4 Bonded Channel Configuration Without Deskew FIFO PCIe ×4 functional modes supports the ×4 bonded channel configuration without deskew FIFO. Figure 2–26 shows the receiver datapath clocking in ×4 channel bonding configurations without deskew FIFO.
Page 716 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–47 Transceiver Channel Datapath Clocking In ×4 bonded channel configurations without deskew FIFO, the CDR in each receiver channel recovers the serial clock from the received data. The serial recovered clock is divided within each channel’s receiver PMA to generate the parallel recovered clock.
Page 717 2–48 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking x8 Bonded Channel Configuration PCIe ×8 functional mode supports the ×8 receiver channel bonding configuration. The eight bonded channels are located in two transceiver blocks, referred to as the master transceiver block and slave transceiver block, with four channels each.
Page 718 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–49 Transceiver Channel Datapath Clocking The CDR in each of the eight receiver channels recovers the serial clock from the received data on that channel. The serial recovered clock is divided within each channel’s receiver PMA to generate the parallel recovered clock.
Page 719 2–50 Chapter 2: Transceiver Clocking in Stratix IV Devices Transceiver Channel Datapath Clocking Figure 2–28. Receiver Channel PMA Directly Interfacing to the User Logic in the FPGA Fabric Channel 3 Receiver Channel PMA Receiver Channel PCS Serializer High-Speed Serial Clock...
Page 720 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–51 FPGA Fabric-Transceiver Interface Clocking FPGA Fabric-Transceiver Interface Clocking The FPGA fabric-Transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver blocks and clock signals from the transceiver blocks to the FPGA fabric.
Page 721 The phase compensation FIFO write clock and read clocks must have exactly the same frequency (0 parts-per-million [PPM] frequency difference). Stratix IV transceivers provide the following two options for selecting the transmitter phase compensation FIFO write clock: “Quartus II-Selected Transmitter Phase Compensation FIFO Write Clock”...
Page 722 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–53 FPGA Fabric-Transceiver Interface Clocking Example 3: Two Groups of Two Identical Channels in a Transceiver Block Example 3 assumes channels 0 and 1, driven by CMU0_PLL in a transceiver block, are identical.
Page 723 2–54 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Figure 2–29 shows the FPGA fabric-Transmitter interface clocking for Example 3. Figure 2–29. FPGA Fabric-Transmitter Interface Clocking for Example 3 Channel 3 Transmitter Channel PCS Transmitter Channel PMA...
Page 724 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–55 FPGA Fabric-Transceiver Interface Clocking Bonded Channel Configuration In ×4 and ×8 bonded channel configurations, all channels within the transceiver block are identical. The Quartus II software automatically drives the write port of the transmitter phase compensation FIFO in all channels with the coreclkout signal.
Page 725 2–56 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write Clock The Quartus II software uses a single tx_clkout signal to clock the transmitter phase compensation FIFO write port of all identical channels within a transceiver block.
Page 726 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–57 FPGA Fabric-Transceiver Interface Clocking Figure 2–31. Sixteen Identical Channels Across Four Transceiver Blocks for Example 4 Transceiver Block GXBR3 Channel [15:12] TX Data Channel 3 tx_coreclk[15:12] and Control Logic Channel 2...
Page 727 2–58 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Because all 16 channels are identical, using a single tx_clkout to clock the transmitter phase compensation FIFO in all 16 channels results in only one global or regional clock resource being used instead of four.
Page 728 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–59 FPGA Fabric-Transceiver Interface Clocking Figure 2–32. Sixteen Identical Channels Across Four Transceiver Blocks for Example 5 Common Clock Driver Transceiver Block GXBR3 Channel [15:12] TX Data Channel 3 tx_coreclk[15:12] and Control...
Page 729 2–60 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Table 2–15 lists the transmitter phase compensation FIFO read clocks that the Quartus II software selects in various configurations. Table 2–15. Transmitter Phase Compensation FIFO Read Clocks...
Page 730 The receiver phase compensation FIFO read clock forms the FPGA fabric-Receiver interface clock. The FIFO write clock and read clock must have exactly the same frequency (0 PPM frequency difference). Stratix IV transceivers provide the following two options for selecting the receiver phase compensation FIFO read clock: ■...
Page 731 2–62 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock If you do not select the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager, the Quartus II software automatically selects the receiver phase compensation FIFO read clock for each channel in that ALTGX instance.
Page 732 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–63 FPGA Fabric-Transceiver Interface Clocking Figure 2–33 shows the FPGA fabric-Receiver interface clocking for Example 6. Figure 2–33. FPGA Fabric-Receiver Interface Clocking for Example 6 Channel 3 Receiver Channel PMA Receiver Channel PCS...
Page 733 2–64 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Non-Bonded Channel Configuration Without Rate Matcher In non-bonded channel configuration without rate matcher, the Quartus II software cannot determine if the incoming serial data in all channels have a 0 PPM frequency difference.
Page 734 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–65 FPGA Fabric-Transceiver Interface Clocking Figure 2–34 shows the FPGA fabric-Receiver interface clocking for non-bonded channel configurations without rate matcher. Figure 2–34. FPGA Fabric-Receiver Interface Clocking for Non-Bonded Channel Configurations Without Rate Matcher...
Page 735 2–66 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking This configuration uses one FPGA global and/or regional clock resource per bonded link for the coreclkout signal. Figure 2–35 shows the FPGA fabric-Receiver interface clocking in ×4 bonded channel configuration.
Page 736 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–67 FPGA Fabric-Transceiver Interface Clocking Example 7: Sixteen Channels Across Four Transceiver Blocks Figure 2–36 shows 16 non-bonded receiver channels without rate matcher, located across four transceiver blocks. The incoming serial data to all 16 channels have a 0 PPM frequency difference with respect to each other.
Page 737 2–68 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Because the recovered clock rx_clkout signals from all 16 channels have a 0 PPM frequency difference, you can use a single rx_clkout to clock the receiver phase compensation FIFO in all 16 channels.
Page 738 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–69 FPGA Fabric-Transceiver Interface Clocking Figure 2–37. Sixteen Identical Channels Across Four Transceiver Blocks for Example 8 Common Clock Driver Transceiver Block GXBR3 Channel [15:12] RX Data Channel 3 rx_coreclk[15:12] and Status...
Page 739 2–70 Chapter 2: Transceiver Clocking in Stratix IV Devices FPGA Fabric-Transceiver Interface Clocking Table 2–17 lists the receiver phase compensation FIFO write clocks that the Quartus II software selects in various configurations. Table 2–17. Receiver Phase Compensation FIFO Write Clocks...
Page 740 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–71 Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric You must ensure that the clock driver for all the connected rx_coreclk ports has a 0 PPM difference with respect to the FIFO write clock in those channels.
Page 741 2–72 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples To use this feature, you must create an ALTGX instance with a single channel in Transmitter Only mode that uses the required CMU PLL or ATX PLL. To create the ALTGX instance, follow these steps: 1.
Page 742 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–73 Configuration Examples Configuration Example 1: Configuring 24 Channels in Basic (PMA Direct) ×N Mode in the EP4S100G5F45 Device Each transceiver block has four regular channels and two CMU channels that you can configure in Basic (PMA Direct) ×N mode.
Page 743 2–74 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples Figure 2–38. Twenty-Four Channels on the Right Side of the EP4S100G5F45 Device Configured in Basic (PMA Direct) ×N Mode for Configuration Example 1 xN_Bottom PLL Cascade Clock Line Transceiver Block GXBR3...
Page 744 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–75 Configuration Examples Configuration Example 2: Configuring Sixteen Identical Channels Across Four Transceiver Blocks This example relates to “User-Selected Receiver Phase Compensation FIFO Read Clock” on page 2–68. Figure 2–39 shows 16 identical transmitter channels located across four transceiver blocks.
Page 745 2–76 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples Table 2–19 lists the Quartus II assignments that you must make for the clocking scheme shown in Figure 2–38. Table 2–19. Quartus II Assignments From top_level/top_xcvr_instance1/altgx_component/tx_clkout[4] tx_dataout[15..0] Assignment Name...
Page 746 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–77 Configuration Examples Figure 2–40. Sixteen Channels Across Four Transceiver Blocks for Configuration Example 3 Transceiver Block GXBR3 Channel [15:12] RX Data Channel 3 rx_coreclk[15:12] and Status Logic Channel 2 Channel 1...
Page 747 2–78 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples Table 2–20 lists the Quartus II assignments that you must make for the clocking scheme shown in Figure 2–40. Table 2–20. Quartus II Assignments for Appendix Example 4 From top_level/top_xcvr_instance1/altgx_component/rx_clkout[9] rx_datain[15..0]...
Page 748 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–79 Configuration Examples 2. Under the Inputs/Lock tab, select Create output file(s) using the 'Advanced' PLL parameters (Figure 2–42). Figure 2–42. Create Output File(s) Using the ‘Advanced’ PLL Parameters Option Use for...
Page 749 2–80 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples 3. Under the Output Clocks tab turn off Use this clock for clk c0. 4. Turn on Use this clock for clk c1 (Figure 2–43). The VCO bypass option is only enabled for clock output c1.
Page 750 Chapter 2: Transceiver Clocking in Stratix IV Devices 2–81 Configuration Examples Document Revision History Table 2–21 lists the revision history for this chapter. Table 2–21. Document Revision History Date Version Changes September 2012 Updated the “Non-Bonded Channel Configurations” section to close FB #65105.
Page 751 2–82 Chapter 2: Transceiver Clocking in Stratix IV Devices Configuration Examples Stratix IV Device Handbook September 2012 Altera Corporation Volume 2: Transceivers...
Page 752 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 753 3–2 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Glossary of Terms ■ “Combination Requirements When You Enable Channel Reconfiguration” on page 3–42 “Combining Transceiver Channels When You Enable the Adaptive Equalization ■ (AEQ) Feature” on page 3–47 “Combination Requirements for Stratix IV Devices”...
Page 754 The following sections describe these requirements. Transmitter Buffer Voltage (V The Stratix IV GX device provides you the option to select 1.4 V or 1.5 V for the V supply through the ALTGX MegaWizard Plug-In Manager. The Stratix IV GT device only allows 1.4 V for the V...
Page 755 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices General Requirements to Combine Channels The Stratix IV GX and GT device provides you the option to select 2.5 V or 3.0 V for the VCCA_L/R supply through the ALTGX MegaWizard Plug-In Manager. The Stratix IV GT device only allows 3.3 V for the V...
Page 756 Dynamic Reconfiguration in Stratix IV Devices chapter. Calibration Clock and Power Down Each calibration block in a Stratix IV GX and GT device is shared by multiple transceiver blocks. If your design uses multiple transceiver blocks, depending on the transceiver banks selected, you must connect the cal_blk_clk and cal_blk_powerdown ports of all channel instances to the same input pin or logic.
Page 757 3–6 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Sharing CMU PLLs Each channel instance can have a different local divider setting. This is a useful option when you intend to run each channel within the transceiver block at different data rates that are derived from the same base data rate using the local divider values /1, /2, and /4.
Page 758 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–7 Sharing CMU PLLs Table 3–3. ALTGX MegaWizard Plug-In Manager Settings for Example 1 Instance General Screen Option Setting (Gbps) What is the effective data rate? 4.25 inst3 Specify base data rate 4.25...
Page 759 3–8 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Sharing CMU PLLs Each of the ALTGX instances has a pll_powerdown port. You must drive the pll_powerdown ports for all the instances from the same logic to enable the Quartus II software to share the same CMU PLL.
Page 760 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–9 Sharing CMU PLLs Figure 3–2 shows the scenario after the Quartus II software combines the transceiver channel instances. Figure 3–2. Combined Instances after Compilation for Example 1...
Page 761 3–10 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Sharing ATX PLLs Sharing ATX PLLs The Quartus II software allows you to share the same ATX PLL for multiple transceiver instances if the following requirements are met: ■...
Page 762 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–11 Combining Transmitter Channel and Receiver Channel Instances Combining Transmitter Channel and Receiver Channel Instances You can create separate transmitter and receiver channel instances and assign the tx_dataout and rx_datain pins of the transmitter and receiver instances, respectively, to the same physical transceiver channel.
Page 763 3–12 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transmitter Channel and Receiver Channel Instances Figure 3–3 Figure 3–4 show the transceiver channel instances before and after compilation. Figure 3–3. ALTGX Transceiver Channel Instances Before Compilation for Example 3 ALTGX Effective Data Rate: 3.125 Gbps...
Page 764 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–13 Combining Transceiver Instances in Multiple Transceiver Blocks Figure 3–4 shows the transceiver channel instances after compilation. Figure 3–4. Combined Transceiver Instances After Compilation for Example 3 Transceiver Block...
Page 765 3–14 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Instances in Multiple Transceiver Blocks Example 4 Consider the design example configuration listed in Table 3–7 with two ALTGX instances. Table 3–7. Two ALTGX Instances for Example 4...
Page 766 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–15 Combining Transceiver Instances in Multiple Transceiver Blocks Figure 3–6 shows the transceiver instances after compilation. Figure 3–6. Combined Transceiver Instances After Compilation for Example 4 Transceiver Block 0 Ch3 of inst0 Effective Data Rate: 4.25 Gbps...
Page 767 Similarly, the right side PLLs can only be cascaded with the transceivers on the right side of the device. Each side of the Stratix IV GX and GT device contains a PLL cascade clock network; a single line network that connects the PLL cascade clock to the transceiver block.
Page 768 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–17 Combining Channels Configured in Protocol Functional Modes Combining Channels Configured in Protocol Functional Modes This section describes how to combine channels for various protocol functional modes. Combining Channels in Bonded Functional Modes This section describes the combination requirements in the two variations of bonded functional modes using transceiver PCS blocks.
Page 769 3–18 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Channels Configured in Protocol Functional Modes Figure 3–7 shows examples of supported and unsupported combinations. Figure 3–7. Examples of Supported and Unsupported Configurations to Combine Instances in Basic ×4 Mode...
Page 770 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–19 Combining Channels Configured in Protocol Functional Modes 4. Using the receiver side of the CMU channels depends on whether you use CMU1 PLL or CMU0 PLL to generate clocks for the bonded ×4 functional mode. If the CMU PLL within the corresponding CMU channel is not available to perform CDR functionality, you cannot configure it as a receiver.
Page 771 3–20 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Channels Configured in Protocol Functional Modes Bonded x8 Functional Mode Bonded ×8 functional mode is similar to bonded ×4 functional mode except that the controls are shared from the physical channel 0 of the master transceiver block. The master is the lower of the two adjacent transceiver blocks selected for the ×8...
Page 772 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–21 Combining Channels Configured in Protocol Functional Modes Each receiver channel configured in Basic ×8 functional mode is clocked independently by the recovered clock from its receiver CDR. You can use the available receiver channels in any configuration.
Page 773 3–22 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Channels Configured in Protocol Functional Modes Figure 3–10. Basic ×8/PCIe ×8 Functional Mode Configuration when Combining Channels (ATX PLL) ATX PLL xN Top Clock Line (3)
Page 774 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–23 Combining Channels Configured in Protocol Functional Modes ■ If the CMU PLL is used to generate clocks for the ×8 bonded functional mode, you can use the CMU0 channel in the slave transceiver block only in Basic (PMA Direct) ×N mode in the single-width configuration.
Page 775 3–17. Combining Channels Using the PCIe hard IP Block with Other Channels The Stratix IV GX and GT device contains an embedded PCIe hard IP block that performs the phyMAC, datalink, and transaction layer functionality specified by PCIe base specification 2.0. Each PCIe hard IP block is shared by two transceiver blocks.
Page 776 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–25 Combining Transceiver Channels in Basic (PMA Direct) Configurations Table 3–8. PCIe Hard IP Block Restrictions When Combining Transceiver Channels with Different Functional and/or Protocol Modes (Part 2 of 2)
Page 777 3–26 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations Combining Multiple Channels Configured in Basic (PMA Direct) ×1 Configurations When you configure a transceiver channel in Basic (PMA Direct) ×1 configuration, the...
Page 778 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–27 Combining Transceiver Channels in Basic (PMA Direct) Configurations Example 5 Consider a design example configuration with a Basic (PMA Direct) ×1 instance with the number of channels set to 7 in the ALTGX MegaWizard Plug-In Manager. With this setting, the ALTGX MegaWizard Plug-In Manager provides 7 bits of gxb_powerdown, rx_analogreset, and pll_powerdown ports.
Page 779 3–28 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations Figure 3–13 shows the conditions after compilation. In this example, the gxb_powerdown and pll_powerdown ports for channels 0 to 4 and channels 5 and 6 are driven from the same logic.
Page 780 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–29 Combining Transceiver Channels in Basic (PMA Direct) Configurations Combining Multiple Instances of Transmitter Only and Receiver Only Configurations in Basic (PMA Direct) ×1 Mode The Quartus II software allows you to combine instances of Transmitter Only and Receiver Only configurations in Basic (PMA Direct) ×1 mode.
Page 781 3–30 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations Figure 3–14 shows Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations before compilation. Figure 3–14. Logical View of the Instances in Basic (PMA Direct) ×1 and Non-Basic (PMA Direct)
Page 782 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–31 Combining Transceiver Channels in Basic (PMA Direct) Configurations Example 7 Consider the example design listed in Table 3–10 for Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations at different data rates.
Page 783 3–32 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations Figure 3–17 shows Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations after compilation. Figure 3–17. Combining Basic (PMA Direct) ×1 and Non-Basic (PMA Direct) Instances in a...
Page 784 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–33 Combining Transceiver Channels in Basic (PMA Direct) Configurations Basic (PMA Direct) ×N Configurations When you configure a transceiver channel in Basic (PMA Direct) ×N configuration, you can enable the Quartus II software to use the ×N lines to provide clocks to the...
Page 785 3–34 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations Figure 3–18 shows the different drivers of the ×N_Top and ×N_Bottom clock lines. Figure 3–18. The ×N_Top and ×N_Bottom Clock Line Connections...
Page 786 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–35 Combining Transceiver Channels in Basic (PMA Direct) Configurations Examples of Combining Multiple Instances of Basic (PMA Direct) ×N Modes The following section describes combining multiple transceiver channel instances in Basic (PMA Direct) ×N mode.
Page 787 3–36 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations You can place channels within a given instance non-contiguously, as shown in Figure 3–19. Figure 3–19. Non-Contiguous Placements of Channels Using Different CMU PLLs for Example 8...
Page 788 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–37 Combining Transceiver Channels in Basic (PMA Direct) Configurations Key Observations ■ Note that channel 5 in inst0 is placed in transceiver block 1 and receives the high-speed clock through the ×N_Top clock line.
Page 789 3–38 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations You can place these two instances in two transceiver blocks, as shown in Figure 3–20. Figure 3–20. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct)
Page 790 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–39 Combining Transceiver Channels in Basic (PMA Direct) Configurations Example 10 Consider the example design listed in Table 3–13 when combining a Basic (PMA Direct) ×N configuration with a non-Basic (PMA Direct) configuration using an ATX PLL.
Page 791 3–40 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels in Basic (PMA Direct) Configurations In this case, the ATX PLL provides the high-speed clock to the transmitter channel of inst1. Therefore, you can combine 10 channels of inst0 and one channel of inst1 in...
Page 792 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–41 Combining Transceiver Channels in Basic (PMA Direct) Configurations You can also combine channels configured in Basic (PMA Direct) ×N mode with bonded ×4 and ×8 functional modes. For example scenarios, refer to Figure 3–8 on...
Page 793 3–42 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combination Requirements When You Enable Channel Reconfiguration Combination Requirements When You Enable Channel Reconfiguration You can configure a transmitter channel to: ■ Switch to an alternate CMU PLL present within the same transceiver block.
Page 794 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–43 Combination Requirements When You Enable Channel Reconfiguration Example 12 shows the requirements. Example 12 Consider that you intend to run four channels within the transceiver block to switch between GIGE and SONET OC48 data rates.
Page 795 3–44 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combination Requirements When You Enable Channel Reconfiguration Table 3–19 lists the assignment for the GXB TX PLL Reconfiguration group for Instance 2 when you compile the design.
Page 796 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–45 Combination Requirements When You Enable Channel Reconfiguration ■ Assign the same GXB TX PLL Reconfiguration group setting value for the tx_dataout ports of all the instances. This is explained in “Combination...
Page 797 3–46 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combination Requirements When You Enable Channel Reconfiguration Figure 3–23 shows the configuration for Example 13. Figure 3–23. Three Transceiver Block Configuration for Example 13 TX3: GIGE x1 Clock Line (2)
Page 798 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–47 Combining Transceiver Channels When You Enable the Adaptive Equalization (AEQ) Feature Create three Instances for steps 1, 2, and 3 with the following parameters: Instance 1 ■...
Page 799 3–48 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Combining Transceiver Channels When You Enable the Adaptive Equalization (AEQ) Feature This section describes the requirements to combine transceiver channels when you enable the AEQ feature. You are not required to enable AEQ in all instances to combine them within the same transceiver block.
Page 800 CMU PLL or 6G ATX PLL. In this case, Stratix IV GT devices follow the same transceiver channel placement rules as Stratix IV GX devices.
Page 801 3–50 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Summary ■ If you enable the PCIe hard IP block using the PCI Express Compiler, the Quartus II software has certain requirements for using the remaining transceiver channels within the transceiver block in the other configurations.
Page 802 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices 3–51 Summary Table 3–23. Document Revision History (Part 2 of 2) Date Version Changes Updated “Transmitter Buffer Voltage (VCCH)” on page 3–2 ■ Added “reconfig_fromgxb and reconfig_togxb Ports” on page 3–3 ■...
Page 803 3–52 Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices Summary Stratix IV Device Handbook September 2012 Altera Corporation Volume 2: Transceivers...
Page 804 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 805 User Reset and Power-Down Signals User Reset and Power-Down Signals Each transceiver channel in the Stratix IV device has individual reset signals to reset its physical coding sublayer (PCS) and physical medium attachment (PMA) blocks. Each CMU PLL in the transceiver block has a dedicated reset signal. The transceiver block also has a power-down signal that affects all the channels and CMU PLLs in the transceiver block.
Page 806 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–3 User Reset and Power-Down Signals Table 4–2 lists the power-down signals available for each CMU PLL transceiver block. Table 4–2. Transceiver Block Power-Down Signals Signal Description Each transceiver block has two CMU PLLs. Each CMU PLL has this dedicated power-down pll_powerdown signal.
Page 807 In PCI Express (PCIe) functional mode, transceiver channels can be either bonded or non-bonded and need to follow a specific reset sequence. The two categories of reset sequences for Stratix IV devices described in this chapter are: ■ “All Supported Functional Modes Except PCIe Functional Mode” on page 4–6—...
Page 808 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–5 Transceiver Reset Sequences The busy signal remains low for the first reconfig_clk clock cycle. It then is asserted from the second reconfig_clk clock cycle. Subsequent de-assertion of the busy signal indicates the completion of the offset cancellation process.
Page 809 (lock-to-data), depending on the logic levels on the rx_locktorefclk and rx_locktodata signals. With the receiver CDR in manual lock mode, you can either configure the transceiver channels in the Stratix IV device in a non-bonded configuration or a bonded configuration. In a bonded configuration, for example in XAUI mode, four channels are bonded together.
Page 810 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–7 Transceiver Reset Sequences Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager in Basic ×4 functional...
Page 811 4–8 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. For XAUI functional mode, with the receiver CDR in automatic lock mode, use the reset...
Page 812 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–9 Transceiver Reset Sequences As shown in Figure 4–4, for the receiver CDR in automatic lock mode configuration, follow these reset steps: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 813 4–10 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. For XAUI functional mode, with the receiver CDR in manual lock mode, use the reset sequence...
Page 814 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–11 Transceiver Reset Sequences As shown in Figure 4–5, for the receiver CDR in manual lock mode configuration, follow these reset steps: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 815 4–12 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and a receiver channel. For Basic ×8 functional mode, with the receiver CDR in automatic lock mode, use the reset...
Page 816 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–13 Transceiver Reset Sequences As shown in Figure 4–6, for the receiver CDR in automatic lock mode, follow these reset steps: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 817 4–14 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. For Basic ×8 functional mode, with the receiver CDR in manual lock mode, use the reset sequence...
Page 818 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–15 Transceiver Reset Sequences As shown in Figure 4–7, for the receiver CDR in manual lock mode, follow these reset steps: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 819 4–16 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Table 4–6. Reset and Power-Down Sequences for Bonded Channel Configurations (Part 2 of 2) Channel Set Up Receiver CDR Mode Refer to “Receiver and Transmitter Channel—Receiver CDR in...
Page 820 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–17 Transceiver Reset Sequences As shown in Figure 4–8, for the receiver in CDR automatic lock mode, follow these reset steps: 1. After power up, wait for the busy signal to be de-asserted.
Page 821 4–18 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences As shown in Figure 4–9, for the receiver CDR in manual lock mode, follow these reset steps: 1. After power up, wait for the busy signal to be asserted.
Page 822 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–19 Transceiver Reset Sequences As shown in Figure 4–10, for the receiver in CDR automatic lock mode, follow these reset steps: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 823 4–20 Chapter 4: Reset Control and Power Down in Stratix IV Devices Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. If you create a Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with...
Page 824 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–21 Transceiver Reset Sequences As shown in Figure 4–11, perform the following reset procedure for the receiver in manual lock mode: 1. After power up, assert pll_powerdown for a minimum period of t...
Page 825 PCIe Functional Mode You can configure PCIe functional mode with or without the receiver clock rate compensation FIFO in the Stratix IV device. The reset sequence remains the same whether or not you use the receiver clock rate compensation FIFO.
Page 826 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–23 Transceiver Reset Sequences PCIe Initialization/Compliance Phase After the device is powered up, a PCIe-compliant device goes through the compliance phase during initialization. In this phase, the PCIe protocol requires the system to be operating at the Gen 1 data rate.
Page 827 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences You can configure the Stratix IV device in ×1, ×4, and ×8 PCIe configurations. The reset sequence described in “PCIe Reset Sequence” on page 4–22 applies to all these multi-lane configurations.
Page 828 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–25 PMA Direct Drive Mode Reset Sequences Basic (PMA Direct) Drive ×N Mode When bonding ×N channels in a Basic (PMA Direct) drive mode configuration, you can reset all bonded channels simultaneously.
Page 829 4–26 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences Transmitter Only Channel with a PLL_L/R The Basic (PMA Direct) mode configuration that requires a PLL_L/R is one where each channel in PMA-Direct mode is identical.
Page 830 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–27 PMA Direct Drive Mode Reset Sequences 3. After the PLL_L/R locks, as indicated by the locked signal going high (marker 4), the transmitter is ready to accept parallel data from the FPGA fabric and subsequently transmitting serial data reliably.
Page 831 4–28 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences Receiver and Transmitter Channel Set-up—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. For PMA Direct drive ×N mode, with the receiver CDR in automatic lock mode, use the reset sequence...
Page 832 (marker 7) for the receiver parallel clock to become stable. At LTD_Auto this point, all the receivers are ready for transferring valid parallel data into the FPGA fabric (until this time, Altera recommends that the user logic that processes this data be under reset). January 2014 Altera Corporation...
Page 833 4–30 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. For PMA Direct drive ×N mode, with receiver CDR in manual lock mode, use the reset sequence...
Page 834 (marker 8) for the receiver parallel clock to become stable. At this LTD_Manual point, all the receivers are ready for transferring valid parallel data into the FPGA fabric (until this time, Altera recommends that the user logic that processes this data be under reset). Basic (PMA Direct) Drive x1 Mode...
Page 835 4–32 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences Receiver and Transmitter Channel Set-Up—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. For Basic (PMA Direct) drive ×1 mode, with receiver CDR in automatic lock mode, use the reset...
Page 836 At this point, all the receivers are ready for transferring valid parallel data into the FPGA fabric (until this time, Altera recommends that the user logic that processes this data be under reset). January 2014 Altera Corporation...
Page 837 4–34 Chapter 4: Reset Control and Power Down in Stratix IV Devices PMA Direct Drive Mode Reset Sequences Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. For Basic (PMA Direct) drive ×1 mode, with receiver CDR in manual lock mode, use the reset...
Page 838 (marker 8) for the receiver parallel clock to be stable. At this LTD_Manual point, all the receivers are ready for transferring valid parallel data into the FPGA fabric (until this time, Altera recommends that the user logic that processes this data be reset). January 2014 Altera Corporation...
Page 839 4–36 Chapter 4: Reset Control and Power Down in Stratix IV Devices Dynamic Reconfiguration Reset Sequences Dynamic Reconfiguration Reset Sequences When using dynamic reconfiguration in data rate divisions in TX or channel and TX CMU PLL select/reconfig modes, use the following reset sequences.
Page 840 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–37 Dynamic Reconfiguration Reset Sequences Reset Sequence when Using Dynamic Reconfiguration with the ‘Channel and TX PLL select/reconfig’ Option Use the example reset sequence shown in Figure 4–21 when you are using the dynamic reconfiguration controller to change the TX PLL settings of the transceiver channel.
Page 841 Power Down The Quartus II software automatically selects the power-down channel feature, which takes effect when you configure the Stratix IV device. All unused transceiver channels and blocks are powered down to reduce overall power consumption. The gxb_powerdown signal is an optional transceiver block signal. It powers down all transceiver channels and all functional blocks in the transceiver block.
Page 842 Chapter 4: Reset Control and Power Down in Stratix IV Devices 4–39 Simulation Requirements Simulation Requirements The following are simulation requirements: ■ The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port is not instantiated, you must assert the tx_digitalreset, rx_digitalreset, and rx_analogreset signals appropriately for correct simulation behavior.
Page 843 4–40 Chapter 4: Reset Control and Power Down in Stratix IV Devices Reference Information Table 4–9. Reference Information (Part 2 of 2) Terms Used in this Chapter Useful Reference Points page 4–3 rx_pll_locked page 4–2 tx_digitalreset Document Revision History Table 4–10 lists the revision history for this chapter.
Page 844 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 845 5–2 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Glossary of Terms Table 5–1. Glossary of Terms Used in this Chapter (Part 2 of 2) Term Description Dynamic reconfiguration controller instance generated by the ALTGX_RECONFIG ALTGX_RECONFIG Instance ™ MegaWizard Plug-In Manager.
Page 846 The dynamic reconfiguration controller is a soft IP that utilizes FPGA-fabric resources. You can use only one controller per transceiver block. You cannot use the dynamic reconfiguration controller to control multiple Stratix IV devices or any off-chip interfaces. Figure 5–1 shows a conceptual view of the dynamic reconfiguration controller architecture.
Page 847 Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Stratix IV GX devices provide two MegaWizard Plug-In Manager interfaces to support dynamic reconfiguration—ALTGX and ALTGX_RECONFIG. ALTGX MegaWizard Plug-In Manager Use the ALTGX MegaWizard Plug-In manager to enable the dynamic reconfiguration settings for the transceiver instances.
Page 848 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–5 Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration ALTGX_RECONFIG MegaWizard Plug-In Manager Use the ALTGX_RECONFIG MegaWizard Plug-In Manager to instantiate the dynamic reconfiguration controller. For more information, refer to the Stratix IV ALTGX_RECONFIG Megafunction User Guide.
Page 849 5–6 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Logical Channel Addressing of Regular Transceiver Channels For a single ALTGX instance connected to the dynamic reconfiguration controller, set the starting channel number to 0. The logical channel addresses of the first channel within the ALTGX instance is 0.
Page 850 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–7 Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Logical Channel Addressing of PMA-Only Channels CMU channels are always PMA-only channels. The regular transceiver channels can be optionally configured as PMA-only channels.
Page 851 5–8 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Figure 5–3. Logical Channel Addressing of PMA-Only Channels ALTGX Instance 1 Basic (PMA Direct) Configuration Starting channel number = 0 Set the What is the number of...
Page 852 Stratix IV device. The maximum number of transceiver channels in the largest Stratix IV device is 48 (24 transceiver channels located in four transceiver blocks on the right side of the device and 24 transceiver channels located in four transceiver blocks on the left side of the device).
Page 853 96th ALTGX instance; therefore, the setting is 380. The highest possible logical channel address assigned to a transceiver channel in a Stratix IV device is the same whether the channel is a regular transceiver channel or a PMA-only channel. Total Number of Channels Option in the ALTGX_RECONFIG Instance You can connect every dynamic reconfiguration controller in a design to either a single ALTGX instance or to multiple ALTGX instances.
Page 854 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–11 Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Connecting the ALTGX and ALTGX_RECONFIG Instances There are two ways to connect the ALTGX_RECONFIG instance to the ALTGX instance in your design: ■...
Page 855 PMA-Only channels. Dynamic Reconfiguration Modes Implementation The modes available for dynamically reconfiguring the Stratix IV transceivers are: ■ “PMA Controls Reconfiguration Mode Details” on page 5–12 “Transceiver Channel Reconfiguration Mode Details” on page 5–19 ■...
Page 856 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–13 Dynamic Reconfiguration Modes Implementation The PMA control ports for the ALTGX_RECONFIG MegaWizard Plug-In Manager are available in the Analog controls screen. You can select the PMA control ports you want to reconfigure. For example, to use tx_vodctrl to write new V...
Page 857 5–14 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Write Transaction Figure 5–5 shows the write transaction waveform when using Method 1. In this example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the logical_channel_address port is 2 bits wide. Also, to initiate the write transaction, you must assert the write_all signal for one reconfig_clk cycle.
Page 858 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–15 Dynamic Reconfiguration Modes Implementation Read Transaction In this example, you want to read the existing V values from the transmit V control registers of the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG instance.
Page 859 5–16 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Write Transaction Assume that you have enabled tx_vodctrl in the ALTGX_RECONFIG MegaWizard Plug-In Manager to reconfigure the V of the transceiver channels. Figure 5–7 shows the write transaction to reconfigure the V Figure 5–7.
Page 860 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–17 Dynamic Reconfiguration Modes Implementation Figure 5–8 shows the read transaction waveform. The transmit V settings written in channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively.
Page 861 5–18 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Write Transaction In this method, the PMA controls are written into all the channels connected to the dynamic reconfiguration controller. Therefore, to write to a specific channel: 1.
Page 862 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–19 Dynamic Reconfiguration Modes Implementation Read Transaction The read transaction in Method 3 is identical to that in Method 2. Refer to “Read Transaction” on page 5–16. Transceiver Channel Reconfiguration Mode Details Table 5–5...
Page 863 5–20 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Memory Initialization File (.mif) As listed in Table 5–5, all the dynamic reconfiguration modes with a check mark in the “.mif Requirement” column use memory initialization files to reconfigure the transceivers.
Page 864 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–21 Dynamic Reconfiguration Modes Implementation 2. Select Fitter settings, then choose More Settings (Figure 5–11). Figure 5–11. Step 2 to Enable .mif Generation 3. In the Option box of the More Fitter Settings page, set the Generate GXB...
Page 865 5–22 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation A .mif is generated for every ALTGX instance defined in the top-level RTL file. The Quartus II software creates the .mif under the <Project_DIR>/reconfig_mif folder. The file name is based on the ALTGX instance name (<instance name>.mif); for example, basic_gxb.mif.
Page 866 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–23 Dynamic Reconfiguration Modes Implementation To reconfigure the transceiver channel or CMU PLL, you must configure the required settings for the transceiver channel or CMU PLL in the ALTGX MegaWizard Plug-In Manager and compile the ALTGX instance. The dynamic reconfiguration controller requires that you write these configured settings through the .mif into the transceiver...
Page 867 5–24 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Whenever a .mif is applied to a channel, the PMA controls for that channel are set to the default settings chosen in the ALTGX instance used for .mif generation.
Page 868 (the transceiver channel specified by the logical_channel_address port), without affecting the remaining transceiver channels controlled by the dynamic reconfiguration controller. You cannot reconfigure the auxiliary transmit (ATX) PLLs in Stratix IV transceivers. Channel Reconfiguration Classifications Table 5–7 lists the classification for channel and CMU PLL reconfiguration mode.
Page 869 5–26 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Figure 5–14 shows the functional blocks that you can dynamically reconfigure using channel and CMU PLL reconfiguration mode. Figure 5–14. Channel and CMU PLL Reconfiguration in a Transceiver Block...
Page 870 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–27 Dynamic Reconfiguration Modes Implementation 5. Provide the starting channel number in the Modes screen. For more information, refer to “Logical Channel Addressing” on page 5–5. 6. Provide the logical reference index of the CMU PLL in the What is the PLL logical reference index? option in the corresponding PLL screen.
Page 871 5–28 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation You can select CMU0 PLL by specifying its identity in the ALTGX MegaWizard Plug-In Manager. This identification is referred to as the logical tx pll value. This value provides a logical identification to CMU0 PLL and associates it with a transceiver channel without requiring the knowledge of its physical location.
Page 872 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–29 Dynamic Reconfiguration Modes Implementation Selecting the Logical Reference Index of the CMU PLL Figure 5–16, transceiver channel 1 listens to CMU0 PLL of the transceiver block. Similarly, transceiver channel 2 listens to CMU1 PLL of the transceiver block.
Page 873 5–30 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation The logical reference index of the CMU0 PLL within a transceiver block is always the complement of the logical reference index of the CMU1 PLL within the same transceiver block.
Page 874 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–31 Dynamic Reconfiguration Modes Implementation Figure 5–17 shows the sharing of channel 0’s tx_clkout between all four regular channels of a transceiver block. Figure 5–17. Option 1 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Page 875 5–32 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Figure 5–18 shows how each transmitter channel’s tx_clkout signal provides a clock to the Transmit Phase Compensation FIFOs of the respective transceiver channels. Figure 5–18. Option 2 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Page 876 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–33 Dynamic Reconfiguration Modes Implementation Option 1: Share a Single Transmitter Core Clock Between Receivers ■ Enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the read clock to the Receive Phase Compensation FIFOs of the remaining receiver channels in the transceiver block.
Page 877 5–34 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Option 2: Use the Respective Channel Transmitter Core Clocks ■ Enable this option if you want the individual transmitter channel’s tx_clkout signal to provide the read clock to its respective Receive Phase Compensation FIFO.
Page 878 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–35 Dynamic Reconfiguration Modes Implementation Figure 5–20 shows the respective tx_clkout of each channel clocking the respective channels of a transceiver block. Figure 5–20. Option 2 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Page 879 5–36 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Figure 5–21 shows the respective rx_clkout of each channel clocking the respective receiver channels of a transceiver block. Figure 5–21. Option 3 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Page 880 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–37 Dynamic Reconfiguration Modes Implementation There are two signals available when you enable the Channel Interface option: ■ tx_datainfull—The width of this input signal depends on the number of channels you set up in the General screen. It is 44 bits wide per channel. This signal is available only for Transmitter only and Receiver and Transmitter configurations.
Page 881 Dynamic Reconfiguration Modes Implementation Table 5–9. tx_datainfull[43:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 3) FPGA Fabric-Transceiver Channel Transmit Signal Description (Based on Stratix IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) tx_datainfull[7:0]: 8-bit data (tx_datain)
Page 882 Dynamic Reconfiguration Modes Implementation Table 5–9. tx_datainfull[43:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 2 of 3) FPGA Fabric-Transceiver Channel Transmit Signal Description (Based on Stratix IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) Two 8-bit Data (tx_datain)
Page 883 Dynamic Reconfiguration Modes Implementation Table 5–9. tx_datainfull[43:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 3 of 3) FPGA Fabric-Transceiver Channel Transmit Signal Description (Based on Stratix IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) Four 8-bit Data (tx_datain)
Page 884 Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) The following signals are used in 8-bit 8B/10B modes:...
Page 885 Dynamic Reconfiguration Modes Implementation Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 2 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) Two 8-bit unencoded Data (rx_dataout)
Page 886 5–43 Dynamic Reconfiguration Modes Implementation Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 3 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) Two 8-bit Data...
Page 887 Dynamic Reconfiguration Modes Implementation Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 4 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) Two 10-bit Data (rx_dataout)
Page 888 Dynamic Reconfiguration Modes Implementation Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 5 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) Four 8-bit un-encoded Data (rx_dataout)
Page 889 Dynamic Reconfiguration Modes Implementation Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 6 of 6) FPGA Fabric-Transceiver Receive Signal Description (Based on Stratix IV GX Supported FPGA Channel Interface Description Fabric-Transceiver Channel Interface Widths) rx_dataoutfull[15], rx_dataoutfull[31], rx_dataoutfull[47], and...
Page 890 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–47 Dynamic Reconfiguration Modes Implementation ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for Channel and CMU PLL Reconfiguration Mode To setup channel and CMU PLL reconfiguration mode in the ALTGX_RECONFIG MegaWizard Plug-In Manager, follow these steps: 1.
Page 891 For more information about reset, refer to the “Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the Reset Control and Power Down in Stratix IV Devices chapter. Channel Reconfiguration with Transmitter PLL Select Mode Details You can reconfigure the data rate of a transceiver channel by switching between a maximum of four transmitter PLLs.
Page 892 For more information about reset, refer to the “Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the Reset Control and Power Down in Stratix IV Devices chapter. Blocks Reconfigured in the Channel Reconfiguration with Transmitter PLL Select Mode The blocks reconfigured in this mode have two types of multiplexers.
Page 893 5–50 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Figure 5–23 shows the multiplexers that you can dynamically reconfigure using channel reconfiguration with transmitter PLL select mode. Figure 5–23. Channel Reconfiguration with Transmitter PLL Select in a Transceiver Block...
Page 894 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–51 Dynamic Reconfiguration Modes Implementation Figure 5–24 shows the multiplexers that are reconfigured when you switch to an additional PLL that is outside the transceiver block. Figure 5–24. Multiplexers that are Reconfigured When you Switch to an Additional PLL...
Page 895 5–52 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation ALTGX MegaWizard Plug-In Manager Setup for Channel Reconfiguration with Transmitter PLL Select Mode Follow steps 1, 2, 4, 7, 8, and 9 described in “ALTGX MegaWizard Plug-In Manager Setup for Channel and CMU PLL Reconfiguration Mode”...
Page 896 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–53 Dynamic Reconfiguration Modes Implementation Selecting the PLL Logical Reference Index for Additional PLLs The PLL logical reference index of additional PLLs outside the transceiver block can only be 2 or 3.
Page 897 For more information about reset, refer to the “Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the Reset Control and Power Down in Stratix IV Devices chapter. CMU PLL Reconfiguration Mode Details Use this mode to reconfigure only the CMU PLL without affecting the remaining blocks of the transceiver channel.
Page 898 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–55 Dynamic Reconfiguration Modes Implementation Transmitter PLL Powerdown During CMU PLL reconfiguration mode, the dynamic reconfiguration controller automatically powers down the selected CMU PLL until it completes reconfiguration. The ALTGX_RECONFIG instance does not provide external ports to control the CMU PLL power down.
Page 899 5–57. For more information about reset, refer to the “Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the Reset Control and Power Down in Stratix IV Devices chapter. Stratix IV Device Handbook...
Page 900 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–57 Dynamic Reconfiguration Modes Implementation Central Control Unit Reconfiguration Mode Details Central control unit reconfiguration mode is a .mif-based mode used to reconfigure the central control unit (CCU) of the transceiver. Use reconfig_mode_sel[] to activate this mode.
Page 901 5–58 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation For more information about input reference clocking, refer to the “Input Reference Clocking” section of the Transceiver Clocking in Stratix IV Devices chapter. The following section describes the clocking requirements to re-use .mifs.
Page 902 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–59 Dynamic Reconfiguration Modes Implementation Figure 5–29 shows the correct input reference clock connections when re-using a .mif. Figure 5–29. Correct Input Reference Clock Connections When Reusing a .mif Stratix IV GX Device...
Page 903 .mif (logical tx pll) Altera recommends keeping track of the transmitter PLL that drives the channel when you configure a transceiver channel in the ALTGX MegaWizard Plug-In Manager. The logical_tx_pll_sel port does not modify transceiver settings on the receiver side.
Page 904 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–61 Dynamic Reconfiguration Modes Implementation Table 5–12 lists the two conditions under which you can re-use .mifs when using the logical_tx_pll_sel and logical_tx_pll_sel_en ports. Table 5–12. Two Conditions Under Which You can Re-Use .mifs (logical_tx_pll_sel and logical_tx_pll_sel_en) Condition 1: Re-use the .mif created for one CMU PLL on...
Page 905 5–62 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Figure 5–31 shows an example scenario where the input reference clock connections to the transceiver channels are based on what you set as the input clock source for each of the CMU transmitter PLLs within a transceiver block.
Page 906 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–63 Dynamic Reconfiguration Modes Implementation Data Rate Division in Transmitter Mode Details You can use data rate division in transmitter mode to modify the data rate of the transmitter channel in multiples of 1, 2, and 4. This dynamic reconfiguration mode is available only for the transmit side and not for the receive side.
Page 907 5–64 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for Data Rate Division in Transmitter Mode Enable the following settings in the ALTGX_RECONFIG MegaWizard Plug-In Manager for data rate division in transmitter mode: 1.
Page 908 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–65 Dynamic Reconfiguration Modes Implementation For this example, the value set in the What is the number of channels controlled by the reconfig controller? option of the ALTGX_RECONFIG MegaWizard Plug-In Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. Also, you must reconfigure the local divider settings of the transmitter channel whose logical channel address is 2'b01.
Page 909 Plug-In Manager. For more information about reset, refer to the “Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the Reset Control and Power Down in Stratix IV Devices chapter. Stratix IV Device Handbook...
Page 910 Dynamic Reconfiguration Modes Implementation Offset Cancellation Feature The Stratix IV GX and GT devices provide an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature (PVT). These variations create an offset in the analog circuit voltages, pushing them out of the expected range.
Page 911 5–68 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation ■ “Logical Channel Addressing—Combination of Regular Transceiver Channels and PMA-Only Channels” on page 5–9 When the device powers up, the dynamic reconfiguration controller initiates offset cancellation on the receiver channel by disconnecting the receiver input pins from the receiver data path.
Page 912 EyeQ EyeQ hardware is available in Stratix IV transceivers to analyze and debug the receiver data recovery path (receiver gain, clock jitter, and noise level). You can use it to monitor the eye width and assess the quality of the incoming signal.
Page 913 EyeQ control block of the ALTGX_RECONFIG instance. You can then access the internal registers of the EyeQ hardware indirectly through the EyeQ control logic. Altera recommends having an input pattern generator and checker to monitor the BER of the received data. Stratix IV Device Handbook...
Page 914 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–71 Dynamic Reconfiguration Modes Implementation Figure 5–36 shows the connections between the EyeQ hardware in the ALTGX instances and the EyeQ control logic in the dynamic reconfiguration controller. Figure 5–36. Connecting ALTGX and ALTGX_RECONFIG Instances with EyeQ Enabled...
Page 915 5–72 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation Table 5–14 lists the EyeQ phase step encoding for the 32 phase steps spanning one unit interval (UI). Table 5–14. EyeQ Phase Step Encoding Desired Phase Step...
Page 916 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–73 Dynamic Reconfiguration Modes Implementation Table 5–15 lists the register memory of the 16-bit EyeQ interface registers. Table 5–15. EyeQ Interface Register Mapping Address Description Control/Status register (EyeQ CSR) Bit [0]—Start: Writing a 1 to this bit instructs the ALTGX_RECONFIG instance to program the ■...
Page 917 5–74 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation 6. Poll the EyeQ interface register 0×0 (the control and status register) and wait for the busy status to be de-asserted. After the status is no longer busy, the data is considered successfully written for write transactions.
Page 918 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–75 Dynamic Reconfiguration Modes Implementation Adaptive Equalization (AEQ) High-speed interface systems require different equalization settings to compensate for changing data rates and backplane losses. Manual tuning of the receiver channel’s equalization stages involves finding the optimal settings through trial and error, and then locking in those values at compile time.
Page 919 5–76 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Modes Implementation The following section describes the connections between the AEQ control block of the ALTGX_RECONFIG instance and the AEQ hardware of the ALTGX instance. Connections Between the ALTGX and ALTGX_RECONFIG Instances Enable the adaptive equalization options in the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers, as explained in the previous section.
Page 920 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–77 Dynamic Reconfiguration Modes Implementation Figure 5–38 shows the aeq_fromgxb[] and aeq_togxb[] connections between multiple ALTGX instances and the dynamic reconfiguration controller. Figure 5–38. Connecting the ALTGX and ALTGX_RECONFIG Instances with AEQ Enabled...
Page 921 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List One Time Mode for a Single Channel Stratix IV GX and GT devices only support one-time adaptation mode for the AEQ feature. Figure 5–39 shows the AEQ timing diagram in this mode.
Page 922 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–79 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 2 of 13) Input/ Port Name Description Output ALTGX and ALTGX_RECONFIG Interface Signals An output port in the ALTGX instance and an input port in the ALTGX_RECONFIG instance.
Page 923 5–80 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 3 of 13) Input/ Port Name Description Output To connect the reconfig_fromgxb port between the ALTGX_RECONFIG instance and multiple ALTGX instances, follow...
Page 924 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–81 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 4 of 13) Input/ Port Name Description Output Used to indicate the busy status of the dynamic reconfiguration controller during offset cancellation.
Page 925 5–82 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 5 of 13) Input/ Port Name Description Output Enabled by the ALTGX_RECONFIG MegaWizard Plug-In Manager when you enable the Use 'logical_channel_address' port for Analog controls reconfiguration option in the Analog controls screen.
Page 926 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–83 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 6 of 13) Input/ Port Name Description Output Analog Settings Control/Status Signals An optional transmit buffer V control signal.
Page 927 5–84 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 7 of 13) Input/ Port Name Description Output An optional pre-emphasis control for pre-tap for the transmit buffer.
Page 928 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–85 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 8 of 13) Input/ Port Name Description Output An optional first post-tap, de-emphasis read control signal for Output Gen2.
Page 929 5–86 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 9 of 13) Input/ Port Name Description Output An optional equalizer DC gain write control. The width of this signal is fixed to 3 bits if you enable either the Use...
Page 930 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–87 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 10 of 13) Input/ Port Name Description Output Transceiver Channel Reconfiguration Control/Status Signals Set the following values at this signal to activate the appropriate dynamic reconfiguration mode: 3’b000 = PMA controls reconfiguration mode.
Page 931 5–88 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 11 of 13) Input/ Port Name Description Output Applicable only in the dynamic reconfiguration modes grouped under the Channel and TX PLL select/reconfig option.
Page 932 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–89 Dynamic Reconfiguration Controller Port List Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 12 of 13) Input/ Port Name Description Output An optional signal that you can use to reset the ALTGX_RECONFIG instance.
Page 933 5–90 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Error Indication During Dynamic Reconfiguration Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 13 of 13) Input/ Port Name Description Output Used for EyeQ control. If asserted, this port indicates that the EyeQ controller is busy with a read or write operation.
Page 934 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–91 Dynamic Reconfiguration Duration TX Data Rate Switch using Local Divider-write operation without input port ■ option: The rate_switch_ctrl input port is not used ■ The reconfig_mode_sel port is set to 3 (if other reconfiguration mode ■...
Page 935 5–92 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Duration PMA Controls Reconfiguration Duration When Using Method 1 The logical_channel_address port is used in Method 1. The write transaction and read transaction duration is as follows: Write Transaction Duration...
Page 936 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–93 Dynamic Reconfiguration Duration For writing values to the following PMA controls, the busy signal is asserted for 520 reconfig_clk clock cycles per channel for each of these controls: tx_preemp_0t (pre-emphasis control pre-tap) ■...
Page 937 5–94 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration (ALTGX_RECONFIG Instance) Resource Utilization Dynamic Reconfiguration Duration for Channel and Transmitter PLL Select/Reconfig Modes Table 5–17 lists the number of reconfig_clk clock cycles it takes for the dynamic reconfiguration controller to reconfigure various parts of the transceiver channel and CMU PLL.
Page 938 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–95 Functional Simulation of the Dynamic Reconfiguration Process Figure 5–40 shows resource utilization in the ALTGX_RECONFIG MegaWizard Plug-In Manager. Figure 5–40. Resource Utilization in the ALTGX_RECONFIG MegaWizard Plug-In Manager Functional Simulation of the Dynamic Reconfiguration Process This section describes the points to be considered during functional simulation of the dynamic reconfiguration process.
Page 939 5–96 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Examples Dynamic Reconfiguration Examples The following examples help to describe the dynamic reconfiguration feature. Example 1 Consider a design with the following configuration: ■ Seven regular transceiver channels in Basic functional mode. You can configure the seven regular transceiver channels from 2.5 Gbps to 5 Gbps and vice versa...
Page 940 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–97 Dynamic Reconfiguration Examples Because this example does not require the use of the alternate CMU transmitter PLL or additional transmitter PLLs, the logical channel addressing remains the same as explained in “Logical Channel Addressing”...
Page 941 5–98 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Examples Figure 5–42 shows how the logical channel addresses of all the channels are set based on what you set as the starting channel number. Figure 5–42. Logical Channel Addresses for Example 1...
Page 942 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–99 Dynamic Reconfiguration Examples Different Dynamic Reconfiguration Modes Involved 1. Channel and CMU PLL reconfiguration mode: is used for reconfiguring the seven regular transceiver channels from one data ■ rate to another using the same CMU0 PLL (in GXBR2) This mode is chosen because both the receiver and transmitter of the regular channels must be re-configured using a single CMU.
Page 943 5–100 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Examples Example 2 Consider a design with the following configuration: ■ Four regular transceiver channels in XAUI configuration. ■ You can configure these channels from the XAUI configuration (the primary configuration) to the PCIe Gen2 ×4 configuration (the secondary configuration)
Page 944 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–101 Dynamic Reconfiguration Examples Table 5–19. Logical Channel Addressing Combination ×4 Bonded Channels (Example 2) (Part 2 of 2) ALTGX Settings and Instances ALTGX_RECONFIG Setting and Instance ALTGX Instance 1 ALTGX_RECONFIG ALTGX Setting...
Page 945 5–102 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Examples Different Dynamic Reconfiguration Modes Involved 1. Channel and CMU PLL reconfiguration mode—used for reconfiguring four regular transceiver channels and the CMU0 PLL (in GXBR0) from XAUI mode to PCIe ×4 mode and vice versa.
Page 946 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices 5–103 Dynamic Reconfiguration Examples Table 5–20. Document Revision History (Part 2 of 2) Date Version Changes Updated Table 5–5, Table 5–6, and Table 5–16. ■ Updated Figure 5–1. ■ Updated the “Transceiver Channel Reconfiguration Mode Details”. “PMA Controls ■...
Page 947 5–104 Chapter 5: Dynamic Reconfiguration in Stratix IV Devices Dynamic Reconfiguration Examples Stratix IV Device Handbook January 2014 Altera Corporation Volume 2: Transceivers...
Page 948 (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 949 A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Stratix IV Device Handbook September 2015 Altera Corporation Volume 2: Transceivers...
Page 950 Stratix IV Device Handbook Volume 3: Transceiver Configuration Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V3-4.4...
Page 951 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 952 Section I. Transceiver Configuration Guide Chapter 1. ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings ............... 1–4 General Screen for the Parameter Settings .
Page 953 Phase 4—Simulating the Design ............2–36 Chapter 3. ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration .
Page 954 Chapter Revision Dates The chapters in this document, Stratix IV Device Handbook Volume 3, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. ALTGX Transceiver Setup Guide for Stratix IV Devices...
Page 955 Chapter Revision Dates Stratix IV Device Handbook January 2014 Altera Corporation Volume 3: Transceiver Configuration Guide...
Page 956 Section I. Transceiver Configuration Guide This section includes the following chapters: Chapter 1, ALTGX Transceiver Setup Guide for Stratix IV Devices ■ ■ Chapter 2, Transceiver Design Flow Guide for Stratix IV Devices ■ Chapter 3, ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Revision History Refer to each chapter for its own specific revision history.
Page 957 I–2 Section I: Transceiver Configuration Guide Stratix IV Device Handbook January 2014 Altera Corporation Volume 3: Transceiver Configuration Guide...
Page 958 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 959 Figure 1–1. MegaWizard Plug-In Manager (Page 1) Figure 1–2 shows the second page of the MegaWizard Plug-In Manager. To use the MegaWizard Plug-In Manager to configure a Stratix IV device, follow these steps: 1. Select Stratix IV as the device family.
Page 960 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–3 4. Name the output file, then Browse to the folder you want to save your file in and click Next. The General screen of the ALTGX MegaWizard Plug-In Manager opens (Figure 1–3).
Page 961 1–4 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Parameter Settings This section describes the options available on the individual pages of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. The MegaWizard Plug-In Manager provides a warning if any of the settings you choose are illegal.
Page 962 Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 1 of 11) ALTGX Setting Description Reference Select GX or GT based on the Stratix IV device used in your design. DC and Switching Which device variation will you Select the speed grade of your device.
Page 963 1–6 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 2 of 11) ALTGX Setting Description Reference Basic In Basic mode, the subprotocols are diagnostic modes.
Page 964 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–7 Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 3 of 11) ALTGX Setting Description Reference PCIe In PCIe mode, there are six subprotocols: Gen1 ×1—The transceiver is configured as a...
Page 965 1–8 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 4 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) Deterministic Latency Serial RapidIO SONET/SDH —...
Page 966 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–9 Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 5 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) Deterministic Latency — Serial RapidIO The number of channels required with the same configuration.
Page 967 1–10 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 6 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) “Basic Single-Width Mode Deterministic Latency Configurations”...
Page 968 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–11 Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 7 of 11) ALTGX Setting Description Reference Basic Deterministic Latency This option determines the FPGA fabric-Transceiver interface width.
Page 969 1–12 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 8 of 11) ALTGX Setting Description Reference SONET/SDH This option selects the FPGA fabric-Transceiver interface width.
Page 970 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–13 Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 9 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) Deterministic Latency If you select the Data Rate option in the What would ■...
Page 971 1–14 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 10 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) If you select the Input Clock Frequency option in the ■...
Page 972 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–15 Parameter Settings Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 11 of 11) ALTGX Setting Description Reference Basic Basic (PMA Direct) The ALTGX MegaWizard Plug-In Manager provides you...
Page 973 1–16 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings PLL/Ports Screen for the Parameter Settings Figure 1–4 shows the PLL/Ports screen of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. Figure 1–4. MegaWizard Plug-In Manager—ALTGX (PLL/Ports Screen) Table 1–2...
Page 974 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–17 Parameter Settings Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 2 of 3) ALTGX Setting Description Reference Enable PLL phase frequency detector (PFD) feedback to “CMU PLL Feedback” section in the...
Page 975 1–18 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 3 of 3) ALTGX Setting Description Reference The receiver digital reset port is available in Receiver only and Receiver and Transmitter “User Reset and Power Down...
Page 976 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–19 Parameter Settings Ports/Calibration Screen for the Parameter Settings Figure 1–5 shows the Ports/Calibration screen of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. Figure 1–5. MegaWizard Plug-In Manager—ALTGX (Ports/Calibration Screen) Table 1–3...
Page 977 1–20 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 2 of 3) ALTGX Setting Description Reference This output port indicates a Create a “TX Phase Compensation FIFO Status...
Page 978 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–21 Parameter Settings Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 3 of 3) ALTGX Setting Description Reference Asserting this signal high powers Create an active high “Input Signals to the Calibration Block”...
Page 979 1–22 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings Loopback Screen for the Parameter Settings Figure 1–6 shows the Loopback screen of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. Figure 1–6. MegaWizard Plug-In Manager—ALTGX (Loopback Screen)
Page 980 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–23 Parameter Settings Table 1–4 lists the available options on the Loopback screen of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation. Table 1–4. MegaWizard Plug-In Manager Options (Lpbk Screen)
Page 981 1–24 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings RX Analog Screen for the Parameter Settings Figure 1–7 shows the RX Analog screen of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. Figure 1–7. MegaWizard Plug-In Manager—ALTGX (RX Analog Screen) Table 1–5...
Page 982 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–25 Parameter Settings Table 1–5. MegaWizard Plug-In Manager Options (RX Analog Screen) (Part 2 of 2) ALTGX Setting Description Reference “Receiver Channel Datapath” section in the What is the receiver common...
Page 983 1–26 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Parameter Settings TX Analog Screen for the Parameter Settings Figure 1–8 shows the TX Analog screen of the ALTGX MegaWizard Plug-In Manager for the Parameter Settings. Figure 1–8. MegaWizard Plug-In Manager—ALTGX (TX Analog Screen)
Page 984 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–27 Parameter Settings Table 1–6 lists the available options on the TX Analog screen of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation. Table 1–6. MegaWizard Plug-In Manager Options (TX Analog Screen) (Part 1 of 2)
Page 985 1–28 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Reconfiguration Settings Table 1–6. MegaWizard Plug-In Manager Options (TX Analog Screen) (Part 2 of 2) ALTGX Setting Description Reference “Programmable Pre-Emphasis” What is the pre-emphasis This option sets the amount of pre-emphasis on...
Page 986 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–29 Reconfiguration Settings Modes Screen for the Reconfiguration Settings Figure 1–9 shows the Modes screen, listing the various dynamic reconfiguration modes available. Figure 1–9. MegaWizard Plug-In Manager—Reconfiguration Settings January 2014 Altera Corporation...
Page 987 1–30 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Reconfiguration Settings Table 1–7 lists the different options available in the Modes screen of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation. Table 1–7. MegaWizard Plug-In Manager Options (Modes Screen) (Part 1 of 2)
Page 988 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–31 Reconfiguration Settings Table 1–7. MegaWizard Plug-In Manager Options (Modes Screen) (Part 2 of 2) ALTGX Setting Description Reference “Guidelines for Specifying Enter the number of input clocks available for selection for the Input Reference Clocks”...
Page 989 1–32 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Reconfiguration Settings Figure 1–10 shows the options available on the Main PLL screen of the ALTGX MegaWizard Plug-In Manager. Figure 1–10. MegaWizard Plug-In Manager Options—Main PLL Screen Table 1–8 lists the available options on the Main PLL screen of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
Page 990 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–33 Reconfiguration Settings Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 2 of 3) ALTGX Setting Description Reference Assign identification numbers to all input reference clocks “Guidelines for Specifying...
Page 991 1–34 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Reconfiguration Settings Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 3 of 3) ALTGX Setting Description Reference These settings are to dynamically reconfigure the transceiver channel to listen to the alternate transmitter PLL.
Page 992 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–35 Reconfiguration Settings Clocking/Interface Screen for the Reconfiguration Settings Figure 1–11 shows the Clocking/Interface screen of the ALTGX MegaWizard Plug-In Manager for the Reconfiguration settings. Figure 1–11. MegaWizard Plug-In Manager Options (Clocking/Interface Screen) Table 1–9...
Page 993 1–36 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Protocol Settings Table 1–9. MegaWizard Plug-In Manager Options (Clocking/Interface Screen) (Part 2 of 2) ALTGX Setting Description Reference Select one of the following available options: “Clocking/Interface How should the transmitters Share a single transmitter core clock between Options”...
Page 994 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–37 Protocol Settings 8B10B Screen for the Protocol Settings Figure 1–12 shows the 8B10B screen of the MegaWizard Plug-In Manager for the Protocol Settings. Figure 1–12. MegaWizard Plug-In Manager—ALTGX (8B10B Screen) Table 1–11...
Page 995 1–38 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Protocol Settings Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 2 of 3) ALTGX Setting Description Reference This is an output status signal that the 8B/10B decoder forwards to the FPGA fabric. This signal indicates whether the decoded 8-bit code group is a data or control code group on this port.
Page 996 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–39 Protocol Settings Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 3 of 3) ALTGX Setting Description Reference Enabling this option in: Single-width mode—the 8-bit D[7:0] or 10-bit ■...
Page 997 1–40 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Protocol Settings Word Aligner Screen for the Protocol Settings Figure 1–13 shows the Word Aligner screen of the MegaWizard Plug-In Manager for the Protocol Settings. Figure 1–13. MegaWizard Plug-In Manager—ALTGX (Word Aligner Screen)
Page 998 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–41 Protocol Settings Table 1–12 lists the available options on the Word Aligner screen of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation. The word aligner and rate matcher operations and patterns are pre-configured for PCIe, GIGE, and XAUI modes, and cannot be altered.
Page 999 1–42 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices Protocol Settings Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 2 of 4) ALTGX Setting Description Reference Use this option in Automatic Synchronization State “Automatic Synchronization State...
Page 1000 Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices 1–43 Protocol Settings Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 3 of 4) ALTGX Setting Description Reference When this option is enabled, the ALTGX MegaWizard Plug-In Manager flips the bit order of the pattern that...

Altera Stratix IV Device Handbook

Table of Contents

Chapter 4 .DSP Blocks in Stratix IV Devices

Chapter 5 .Clock Networks and Plls in Stratix IV Devices

Chapter 6 .I/O Features in Stratix IV Devices

Chapter 13 .Power Management in Stratix IV Devices

Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices

Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices

Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

Chapter 11 .SEU Mitigation in Stratix IV Devices

Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices

. Altgx_Reconfig Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration/Additional Information

Chapter 3. ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration

Table of Contents

Chapter 1. DC and Switching Characteristics for Stratix IV Devices

Chapter 2. Addendum to the Stratix IV Device Handbook

Quick Links

Chapters

Related Manuals for Altera Stratix IV

Summary of Contents for Altera Stratix IV