Altera Stratix GX Manuals

Manuals and User Guides for Altera Stratix GX. We have 1 Altera Stratix GX manual available for free PDF download: User Manual

Altera Stratix GX User Manual

Altera Stratix GX User Manual (318 pages)

Brand: Altera | Category: Transceiver | Size: 8.24 MB

Table of Contents

Table of Contents
3
About this User Guide

7
- How to Contact Altera
  7
- Typographic Conventions
  8
Chapter 1. Introduction

9
- Gigabit Transceiver Block Highlights
  9
- Transceiver Block Architecture
  10
  - Analog Section Overview
    10
  - Digital Overview
    11
- Modes of Operation
  13
  - Basic Mode
    13
  - SONET Mode
    14
  - XAUI Mode
    15
  - Gige Mode
    16
  - Loopback
    17
  - Built-In Self Test
    17
Chapter 2. Stratix GX Analog Description

19
- Introduction
  19
- Transmitter Analog
  20
  - Transmitter Buffer
    20
  - Serializer (Parallel-To-Serial Converter)
    20
- Receiver Analog
  27
  - Receiver Input Buffer
    27
  - Receiver PLL
    30
  - Clock Recovery Unit
    34
  - Deserializer (Serial-To-Parallel Converter)
    37
- Megawizard Analog Features
  38
  - Megawizard Analog Feature Considerations
    38
Chapter 3. Basic Mode

47
- Introduction
  47
- Basic Mode Receiver Architecture
  48
  - Word Aligner
    48
  - 8B/10B Decoder
    55
  - Byte Deserializer
    59
  - Receiver Phase Compensation FIFO Buffer
    61
- Basic Mode Transmitter Architecture
  62
  - Transmitter Phase Compensation FIFO Buffer
    62
  - Byte Serializer
    63
  - 8B/10B Encoder
    63
- Basic Mode Clocking
  66
- Basic Mode Megawizard Plug-In
  75
  - Basic Mode Megawizard Plug-In Manager Considerations
    75
  - Basic Mode Altgxb Megawizard Options
    75
Chapter 4. SONET Mode

83
- Introduction
  83
- SONET Mode Receiver Architecture
  84
  - Word Aligner
    84
  - Byte Deserializer
    90
  - Receiver Phase Compensation FIFO Module
    92
- SONET Mode Transmitter Architecture
  93
  - Transmitter Phase Compensation FIFO Buffer
    93
  - Byte Serializer
    94
- SONET Mode Clocking
  94
  - SONET Mode Channel Clocking
    94
  - SONET Mode Inter-Transceiver Block Clocking
    99
- SONET Mode Megawizard Plug-In Manager
  105
  - SONET Mode Megawizard Considerations
    105
  - SONET Mode Altgxb Megawizard Options
    105
Chapter 5. XAUI Mode

113
- Introduction
  113
- XAUI Mode Receiver Architecture
  117
  - Word Aligner
    118
  - Channel Aligner
    121
  - Rate Matcher
    123
  - 8B/10B Decoder
    123
  - PCS - XGMII Code Conversion
    127
  - Byte Deserializer
    127
  - Receiver Phase Compensation FIFO Module
    130
- XAUI Mode Transmitter Architecture
  130
  - Transmitter Phase Compensation FIFO Module
    130
  - Byte Serializer
    131
  - XGMII Character to PCS Code-Group Mapping
    132
  - 8B/10B Encoder
    133
- XAUI Mode Clocking
  136
  - XAUI Mode Channel Clocking
    136
  - XAUI Inter-Transceiver Block Clocking
    140
  - Xaui Mode Clocking
    144
- XAUI Mode Megawizard Plug-In Manager
  146
  - XAUI Mode Megawizard Considerations
    146
  - XAUI Mode Altgxb Megawizard Options
    146
Chapter 6. Gige Mode

155
- Introduction
  155
  - Word Aligner
    158
  - Rate Matcher
    163
  - 8B/10B Decoder
    165
  - Receiver Phase Compensation FIFO Buffer
    168
- Gige Mode Transmitter Architecture
  168
  - Transmitter Phase Compensation FIFO Buffer
    169
  - Gige Transmitter Synchronization
    170
  - Idle Generation
    170
  - 8B/10B Encoder
    171
- Gige Mode Clocking
  174
- Design Example
  192
  - Design Description
    192
  - Simulation Waveform & Hardware Verification Results
    198
Chapter 7. Loopback Modes

201
- Introduction
  201
- Serial Loopback
  201
- Parallel Loopback
  202
- Reverse Serial Loopback
  203
Chapter 8. Stratix GX Built-In Self Test (BIST)

205
- Introduction
  205
- Pattern Generator
  206
  - PRBS Mode Generator
    206
  - Incremental Mode Generator
    207
  - High-Frequency Mode Generator
    207
  - Low-Frequency Mode Generator
    208
  - MIX-Frequency Mode Generator
    209
- Pattern Verifier
  209
  - PRBS Mode Verifier
    209
  - Incremental Mode Verifier
    210
- Design Examples
  211
Chapter 9. Reset Control & Power down

227
- Introduction
  227
- Power on Reset (POR)
  227
- USER Reset & Enable Signals
  227
- Recommended Resets
  230
  - Receiver & Transmitter Reset
    230
  - Receiver Reset
    258
  - Transmitter Reset
    278
- Power down
  283
Appendix A. Data & Control Codes

285
- 8B/10B Code
  285
  - Code Notation
    285
  - Disparity Calculation
    285
  - Supported Codes
    287
Appendix B. Ports & Parameters

297
- Input Ports
  297
- Output Ports
  301
- Parameter Descriptions
  305
Appendix C. REFCLKB Pin Constraints

311
- Known Issues
  311
  - Quartus II Software Messages
    313
  - Recommendations
    315

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