Guidelines To Debug System Level Issues - Altera Stratix IV Device Handbook

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Guidelines to Debug Transceiver-Based Designs
■ Use SignalTap to verify the behavior of the user logic and the transceiver interface
signals. If you have FPGA I/O pins available for debug, you can also use the
external logic analyzer to debug the functionality of the device.
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Verify the interconnect on the receive side by configuring the transceiver in reverse
■
serial loopback mode. In this case, the recovered data from the receiver channel is
sent to the transmitter buffer. To configure a transceiver channel operating in a
different configuration to reverse serial loopback mode, use the dynamic
reconfiguration controller.
■ Check whether the transceiver FPGA fabric interface clocking schemes follow the
recommendations provided in the "FPGA Fabric-Transceiver Interface Clocking"
section in the
Ensure that you have used the recommended transceiver reset sequence.
■

Guidelines to Debug System Level Issues

If you have determined that the logic in the FPGA fabric is functionally correct, check
for system level issues:
■ Check the voltage ripple across the 2 k resistor that is connected to the RREF pin.
The voltage ripple must be less than 60 mv.
■ Measure the eye on the near-end and far-end of the transmitter to understand the
jitter added by the transmitter and interconnect.
■
■
■
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■ Measure signals on the traces (no connector) using a high-impedance differential
probe with short leads.
February 2011 Altera Corporation
For more information, refer to the
Analyzers chapter in volume 3 of the Quartus II Handbook.
To use these features, you must connect the JTAG configuration pins in the
FPGA.
Transceiver Clocking in Stratix IV Devices
Ensure that the high-speed scopes you use for measurement have sufficient
bandwidth (the bandwidth rating on the scope and cables must be at least
three times the serial data rate).
Check whether the eye meets the eye-mask requirements if specified by the
protocol application.
Use scopes that provide information on the different jitter components to
understand the possible source of the increased jitter. For example, increased
intersymbol interface (ISI) indicates potential bandwidth limitations on the
interconnect.
Some scopes, such as Agilent 86100C DCA, require pre-defined patterns
(for example, PRBS7 or PRBS23) to provide jitter components.
In-System Debugging Using External Logic
chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
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