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Stratix Device Handbook, Volume 2

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http://www.altera.com

S5V2-3.5

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Page 1 Stratix Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com S5V2-3.5...
Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.
Page 3: Table Of Contents
How to Contact Altera ........................... xv Typographic Conventions ........................xvi Section I. Clock Management Revision History ........................Section I–1 Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices Introduction ............................1–1 Enhanced PLLs ............................1–5 Clock Multiplication & Division ....................1–9 External Clock Outputs .........................
Page 4 Guidelines ............................1–56 Conclusion ............................1–56 Section II. Memory Revision History ........................Section II–1 Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Introduction ............................2–1 TriMatrix Memory ..........................2–1 Clear Signals ............................2–3 Parity Bit Support ..........................2–3 Byte Enable Support ........................
Page 5 Conclusion ............................3–27 Section III. I/O Standards Revision History ........................Section III–1 Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices Introduction ............................4–1 Stratix & Stratix GX I/O Standards ....................4–1 3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) - EIA/JEDEC Standard JESD8-B . 4–2 3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B ................
Page 6 Auto Placement & Verification of Selectable I/O Standards ........... 4–41 Conclusion ............................4–42 More Information ..........................4–42 References ............................. 4–42 Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices Introduction ............................5–1 Stratix I/O Banks ........................... 5–1 Stratix Differential I/O Standards ....................5–2 Stratix Differential I/O Pin Location .....................
Page 7 SERDES Bypass Mode ........................5–70 Summary ............................... 5–75 Section IV. Digital Signal Processing (DSP) Revision History ........................Section IV–1 Chapter 6. DSP Blocks in Stratix & Stratix GX Devices Introduction ............................6–1 DSP Block Overview ..........................6–2 Architecture ............................6–5...
Page 8 Chapter 7. Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Introduction ............................7–1 Stratix & Stratix GX DSP Block Overview ..................7–1 TriMatrix Memory Overview ......................7–4 DSP Function Overview ........................7–5 Finite Impulse Response (FIR) Filters ....................7–5 FIR Filter Background ........................
Page 9 Contents Contents Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Introduction ............................8–1 Related Links ............................. 8–1 10-Gigabit Ethernet ..........................8–1 Interfaces ..............................8–5 XSBI ..............................8–5 XGMII ............................... 8–13 XAUI ..............................8–19 I/O Characteristics for XSBI, XGMII & XAUI ................. 8–21 Software Implementation ......................
Page 10 Jam STAPL Programming & Test Language ................11–42 Configuring Using the MicroBlaster Driver .................. 11–51 Device Configuration Pins ....................... 11–51 Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices Introduction ............................12–1 Remote Configuration Operation ...................... 12–1 Remote System Configuration Modes ..................12–3 Remote System Configuration Components ................
Page 11 Contents Contents Section VII. PCB Layout Guidelines Revision History ........................Section VII–1 Chapter 13. Package Information for Stratix Devices Introduction ............................13–1 Device & Package Cross Reference ....................13–1 Thermal Resistance ..........................13–2 Package Outlines ..........................13–3 484-Pin FineLine BGA - Flip Chip ....................13–4 672-Pin FineLine BGA - Flip Chip ....................
Page 12 Contents Stratix Device Handbook, Volume 2 Altera Corporation...
Page 13: Chapter Revision Dates
Chapter Revision Dates The chapters in this book, Stratix Device Handbook, Volume 2, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices...
Page 14 Chapter Revision Dates Stratix Device Handbook, Volume 2 Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices Revised: July 2005 Part number: S52012-3.0 Chapter 11. Configuring Stratix & Stratix GX Devices Revised: July 2005 Part number: S52013-3.2 Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices...
Page 15: About This Handbook
Numerous links, shown in green text, which allow you to jump to related information. How to Contact For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on Altera this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.
Page 16: Typographic Conventions
Typographic Conventions Stratix Device Handbook, Volume 2 Typographic This document uses the typographic conventions shown below. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters. Example: Save As dialog box.
Page 17: Section I. Clock Management
Note 3 added to columns 11 and 12 in Table 1–1. ● Deleted “Stratix GX Clock Input Sources for Enhanced and Fast PLLs” table. Deleted “Stratix GX Global and Regional Clock Output Line Sharing for ● Enhanced and Fast PLLS” table.
Page 18 Clock Management Stratix Device Handbook, Volume 2 Chapter Date/Version Changes Made November 2003, v2.2 ● Updated the “Lock Detect” section. October 2003, v2.1 ● Updated the “VCCG & GNDG” section. ● Updated Figure 1–14. July 2003, v2.0 ● Updated clock multiplication and division, spread spectrum, and Notes 1 and 8 in Table 1-3.
Page 19: Introduction
(PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX device: enhanced PLLs and fast PLLs. Each device has up to four...
Page 20 Introduction Table 1–2. Stratix GX Device PLL Availability Fast PLLs Enhanced PLLs Device EP1S10C EP1S10D EP1S25C EP1S25D EP1S25F EP1S40D EP1S40G 1–2 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 21 Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. On Stratix GX devices, PLLs 3, 4, 9, and 10 are not available for general-purpose use.
Page 22 Introduction Figure 1–1 shows a top-level diagram of the Stratix device and PLL floorplan. Figure 1–2 shows a top-level diagram of the Stratix GX device and PLL floorplan. See “Clocking” on page 1–39 for more detail on PLL connections to global and regional clocks.
Page 23: Enhanced Plls
LVDSCLK0 HSSI CLK0-3 PLLs HSSI LVDSCLK1 CLK4-7 Enhanced PLLs Stratix and Stratix GX devices contain up to four enhanced PLLs with advanced clock management features. Figure 1–3 shows a diagram of the enhanced PLL. Altera Corporation 1–5 July 2005 Stratix Device Handbook, Volume 2...
Page 24 These four counters and external outputs are available in PLLs 5 and 6. This connection is only available on EP1SGX40 Stratix GX devices and EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Page 25 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–4 shows all the possible ports of the enhanced PLLs. Figure 1–4. Enhanced PLL Signals Physical Pin pllenable clk[5..0] Signal Driven by Internal Logic inclk0 Signal Driven to Internal Logic inclk1...
Page 26 Serial input data stream for the real-time PLL Logic array Reconfiguration scandata control feature circuit Serial shift register reset clearing all registers in Logic array Reconfiguration scanaclr the serial shift chain⎯ active high circuit 1–8 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 27: Clock Multiplication & Division
Clock Multiplication & Division Each Stratix and Stratix GX device enhanced PLL provides clock synthesis for PLL output ports using m/(n × post-scale counter) scaling factors. The input clock is divided by a pre-scale counter, n, and is then multiplied by the m feedback factor.
Page 28: External Clock Outputs
MegaWizard Plug-In Manager. External Clock Outputs Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 1–5. 1–10 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 29 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–5. External Clock Outputs for PLLs 5 & 6 From IOE (1), (2) pll_out0p (3), (4) e0 Counter pll_out0n (3), (4) From IOE (1) From IOE (1) pll_out1p (3), (4) e1 Counter...
Page 30 I/O Standard INCLK FBIN PLLENABLE EXTCLK LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 1–12 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 31 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK 3.3-V GTL+ 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II...
Page 32: Clock Feedback
Enhanced PLLs Stratix and Stratix GX devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases.
Page 33: Lock Detect
PLL is not important in your design, the PLL need not be reset. See the Stratix FPGA Errata Sheet for more information on implementing the gated lock signal in your design. Altera Corporation 1–15...
Page 34: Programmable Duty Cycle
PLL out of lock. The VCO sets back to its nominal setting (~700 MHz). When driven low again, the PLL resynchronizes to its input as it relocks. If the target VCO frequency is below this nominal 1–16 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 35 General-Purpose PLLs in Stratix & Stratix GX Devices frequency, then the output frequency starts at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks.
Page 36: Programmable Bandwidth
It is determined by the − 3-dB frequency of the closed-loop gain in the PLL or approximately the unity gain point for open loop PLL response. As Figure 1–8 shows, these points correspond to approximately the same frequency. 1–18 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 37 A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A low- bandwidth PLL filters out reference clock jitter, but increases lock time. Stratix device enhanced PLLs allow you to control the bandwidth over a Altera Corporation 1–19...
Page 38 Applications that require clock switchover (such as TDMA, frequency hopping wireless, and redundant clocking) can benefit from the programmable bandwidth feature of the Stratix and Stratix GX PLLs. The bandwidth and stability of such a system is determined by a number...
Page 39 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–10. High-Bandwidth PLL Lock Time Lock Time = 4 μs Frequency (MHz) Time (μs) A high-bandwidth PLL may benefit a system with two cascaded PLLs. If the first PLL uses spread spectrum (as user-induced jitter), the second PLL needs a high bandwidth so it can track the jitter that is feeding it.
Page 40 Enhanced PLLs Figure 1–11. Effect of Low Bandwidth on Clock Switchover Frequency (MHz) Input Clock Stops Re-lock Initial Lock Switchover Time (μs) 1–22 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 41 PLL’s bandwidth. Most loop filters are made up of passive components, such as resistors and capacitors, which take up unnecessary board space and increase cost. With Stratix and Stratix GX device enhanced PLLs, all the components are contained within the device to increase performance and decrease cost.
Page 42 High bandwidth is set at 2 Mhz If you choose Auto bandwidth, the Quartus II software chooses the PLL settings and you can get a bandwidth setting outside the 150-Khz to 2-Mhz range. 1–24 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 43: Clock Switchover
Megafunction User Guide. Clock Switchover For more information on implementing clock switchover, see AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices. Spread-Spectrum Clocking Digital clocks are generally square waves with short rise times and a 50% duty cycle.
Page 44 Spread-spectrum technology would benefit a design with high EMI emissions and/or strict EMI requirements. Device-generated EMI is dependent on frequency, output voltage swing amplitude, and slew rate. For example, a design using LVDS already has low EMI emissions 1–26 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 45 EMI rejection within the signal. Therefore, this situation may not require spread-spectrum technology. Description Stratix and Stratix GX device enhanced PLLs feature spread-spectrum technology to reduce the EMI emitted from the device. The enhanced PLL provides up to a 0.5% down spread (–0.5%) using a triangular, also known as linear, modulation profile.
Page 46 × n percent spread = (f )/(m VCOmax VCOmin VCOmax The maximum and minimum VCO frequency is defined as: ) × f = (m VCOmax ) × f = (m VCOmin 1–28 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 47 PLL’s bandwidth to low. Designs cannot use spread-spectrum PLLs with the programmable bandwidth feature. Stratix and Stratix GX devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the downstream PLL.
Page 48: Pll Reconfiguration
Therefore, the system never exceeds the maximum clock speed. To maintain reliable communication, the entire system/subsystem should use the Stratix or Stratix GX device as the clock source. Communication could fail if the Stratix or Stratix GX logic array is clocked by the spread-spectrum clock, but the data it receives from another device is not.
Page 49: Fast Plls
CCIO and PLL5_OUT3n outputs from PLL 6. Fast PLLs Stratix devices contain up to eight fast PLLs and Stratix GX devices contain up to four fast PLLs. Both device PLLs have high-speed differential I/O interface ability along with general-purpose features.
Page 50 It cannot be driven by internally-generated global signals. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix and Stratix GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
Page 51 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–18 shows all possible ports related to fast PLLs. Figure 1–18. Fast PLL Ports & Physical Destinations Fast PLL Signals pllena clk[2..0] inclk0 locked areset pfdena Physical Pin Signal Driven by Internal Logic...
Page 52: Clock Multiplication & Division
PLL in that bank. See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device Handbook, Volume 2 for output standard support.
Page 53: Phase Shifting
SSTL-3 Class II AGP (1× and 2×) Phase Shifting Stratix and Stratix GX device fast PLLs have advanced clock shift ability to provide programmable phase shift. These parameters are set in the Quartus II software. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry.
Page 54: Programmable Duty Cycle
The areset signals are reset/resynchronization inputs for each fast PLL. The Stratix and Stratix GX devices can drive these input signals from an input pin or from LEs. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO sets back to its nominal setting (~700 MHz).
Page 55: Pins
General-Purpose PLLs in Stratix & Stratix GX Devices resynchronizes to its input clock as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency starts at a higher value then desired as it locks.
Page 56 Analog power for PLL 9. Connect this pin to 1.5 V, even if the PLL is not used. VCCA_PLL9 Guard ring power for PLL 9. Connect this pin to 1.5 V, even if the PLL is not VCCG_PLL9 used. 1–38 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 57: Clocking
Table 1–13: PLLs 3, 4, 9, and 10 are not available on Stratix GX devices for general-purpose configuration. These PLLs are part of the HSSI block. See AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices for more information.
Page 58 Regional Clock Network There are four regional clock networks within each quadrant of the Stratix or Stratix GX device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and...
Page 59: Clock Input Connections
General-Purpose PLLs in Stratix & Stratix GX Devices RCLK[12..15] are in the bottom-right quadrant. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant.
Page 60 Clocking Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. Stratix GX devices use PLLs 3 and 4 in the HSSI block only. A multiplexer chooses one of two possible CLK pins to drive each PLL. This multiplexer is not a clock switchover multiplexer and is only used for clock input connectivity.
Page 61: Clock Output Connections
You can connect each fast PLL 1, 2, 3, or 4 outputs (g0, l0, and l1) to either a global or a regional clock. (PLLs 3 and 4 are not available on Stratix GX devices.) There is line sharing between clock pins,...
Page 62 CLK and pins drive when bypassing FPLLCLK the PLL. Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 1 of 2) EP1S40 (5), EP1S30, EP1S40, EP1S60 & EP1S60 &...
Page 63 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 2 of 2) EP1S40 (5), EP1S30, EP1S40, EP1S60 & EP1S60 & All Devices EP1S80 Devices Only...
Page 64 Clocking Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1) CLK Pins FPLLCLK Clock Network 10 11 12 13 14 15 GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 GCLK8 GCLK9 GCLK10...
Page 65 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1) CLK Pins FPLLCLK Clock Network 10 11 12 13 14 15 RCLK13 RCLK14 RCLK15 Notes to Table 1–16:...
Page 66 PLL. PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix GX devices and are not available for this use. When using a fast PLL to compensate for clock delays to drive logic on...
Page 67 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–22. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs E[0..3] PLL 5 PLL 11 L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1...
Page 68: Board Layout
PLL. Isolate the power connected to VCCA from the power to the rest of the Stratix and Stratix GX device or any other digital device on the board. You can use one of three different methods of isolating the VCCA...
Page 69 Decouple each V pin with a 0.1-μF and 0.001-μF parallel combination of ceramic capacitors located as close as possible to the Stratix or Stratix GX device. You can connect the GNDA pins directly to the same ground plane as the device’s digital ground.
Page 70: Vccg & Gndg
Board Layout Figure 1–24. PLL Power Schematic for Stratix or Stratix GX PLLs Ferrite Bead 1.5-V Supply 10 μF PLL<PLL number>_VCCA 0.1 μF 0.001 μF PLL<PLL number>_GNDA CCINT PLL<PLL number>_VCCG Repeat for Each PLL PLL<PLL number>_GNDG Power and Ground Set Stratix Device VCCG &...
Page 71: External Clock Output Power
General-Purpose PLLs in Stratix & Stratix GX Devices External Clock Output Power Enhanced PLLs 5 and 6 also have isolated power pins for their dedicated external clock outputs (VCC_PLL5_OUTA and VCC_PLL5_OUTB, or VCC_PLL6_OUTA and VCC_PLL6_OUTB, respectively). PLLs 5 and 6 both have two banks of outputs.
Page 72 Note to Figure 1–25: These pins apply to PLL 5. The figure for PLL 6 is similar, except that the pin names begin with the prefix PLL6 instead of PLL5. 1–54 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 73 1–26. Decouple the isolated power pins with a 0.1-μF and a 0.001-μF parallel combination of ceramic capacitors located as close as possible to the Stratix device. Figure 1–26. Stratix PLL External Clock Output Power Ball Connections Note (1) CCIO Supply VCC_PLL5_OUTA 0.1 μF...
Page 74: Guidelines
Use phase shift to skew clock edges with respect to each other for best jitter performance. Delay shift (time delay elements) are no longer supported in Stratix PLLs. Use the phase shift feature to implement the desired time shift. ■...
Page 75: Section Ii. Memory
Chapter 3, External Memory Interfaces in Stratix & Stratix GX Devices The QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices chapter is removed in this version of the Stratix Device Handbook. The information is available in AN 349: Interfacing QDR SRAM with Stratix and Stratix GX Devices.
Page 76 June 2006, v3.3 ● Changed the name of the chapter from External Memory Interfaces to External Memory Interfaces in Stratix & Stratix GX Devices to reflect its shared status between those device handbooks. ● Added cross reference regarding frequency limits for 72 and 90 phase shift for DQS.
Page 77: Chapter 2. Trimatrix Embedded Memory Blocks In Stratix & Stratix Gx Devices
Offering up to 10 Mbits of RAM and up to 12 terabits per second of device memory bandwidth, the TriMatrix memory structure makes the Stratix and Stratix GX families ideal for memory-intensive applications. TriMatrix TriMatrix memory structures can implement a wide variety of complex memory functions.
Page 78 The rden register on the M512 memory block does not have a clear port. On the M4K block, asserting the clear port of the rden and byte enable registers drives the output of these registers high. 2–2 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 79: Clear Signals
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices The extremely high memory bandwidth of the Stratix and Stratix GX device families is a result of increased memory capacity and speed. Table 2–2 shows the memory capacity for TriMatrix memory blocks in each Stratix device.
Page 80: Byte Enable Support
Notes to Table 2–4: Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32 modes. 2–4 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 81 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices M-RAM Blocks M-RAM blocks support byte enables for the × 16, × 18, × 32, × 36, × 64, and × 72 modes. In the × 128 or × 144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) combine to form the necessary 16 byte enables.
Page 82 Note to Figure 2–1: For more information on simulation output when a read-during-write occurs at the same address location, see “Read-During-Write Operation at the Same Address” on page 2–25. 2–6 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 83: Using Trimatrix Memory
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Using TriMatrix The TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system Memory performance. All TriMatrix memory blocks are pipelined, meaning that all inputs are registered, but outputs are either registered or combinatorial.
Page 84: Implementing Simple Dual-Port Mode
] rden wren q[ ] inclock outclock inclocken outclocken inaclr outaclr Note to Figure 2–4: Simple dual-port RAM supports read/write clock mode in addition to the input/output clock mode shown. 2–8 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 85 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices TriMatrix memory supports mixed-width configurations, allowing different read and write port widths. When using mixed-width mode, the LSB is written to or read from first. For example, take a RAM that is set up in mixed-width mode with write data width ×8 and read data width ×2.
Page 86 I/O standards using global or regional clocks. For more information on Stratix device I/O structure see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. For more information on Stratix GX device I/O structure see the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 87: Implementing True Dual-Port Mode
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices M-RAM blocks have one write enable signal in simple dual-port mode. To perform a write operation, the write enable is held high. The M-RAM block is always enabled for read operation. If the read address and the write address select the same address location during a write operation, the M-RAM block output is unknown.
Page 88 Port A 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 512 × 9 256 × 18 × × × × × × × 2–12 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 89 See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 for the maximum synchronous write cycle time.
Page 90: Implementing Shift-Register Mode
M512 block and 36 bits for the M4K block. If a larger shift register is required, the memory blocks can be cascaded together. M-RAM blocks do not support the shift-register mode. 2–14 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 91: Implementing Rom Mode
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift-register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle.
Page 92: Implementing Fifo Buffers
B controls all registers on the port B side. Each port also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2–9 shows a TriMatrix memory block in independent clock mode. 2–16 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 93 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Figure 2–9. Independent Clock Mode Note (1), Note to Figure 2–9: Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
Page 94: Input/Output Clock Mode
Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2–10 2–11 show the memory block in input/output clock mode for true and simple dual-port modes, respectively. 2–18 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 95 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Figure 2–10. Input/Output Clock Mode in True Dual-Port Mode Note (1) Note to Figure 2–10: Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
Page 96 For more information on the MultiTrack™ interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 97: Read/Write Clock Mode
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Read/Write Clock Mode The TriMatrix memory blocks can implement read/write clock mode for simple dual-port memory. This mode can use up to two clocks. The write clock controls the block’s data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden.
Page 98 2–12: For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 99: Single-Port Mode
2–13: For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 100: Selecting Trimatrix Memory Blocks
Designing With TriMatrix Memory For information on the difference between APEX-style memory and TriMatrix memory, see the Transitioning APEX Designs to Stratix Devices chapter. Selecting TriMatrix Memory Blocks The Quartus II software automatically partitions user-defined memory into embedded memory blocks using the most efficient size combinations.
Page 101: Power-Up Conditions & Memory Initialization
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Power-up Conditions & Memory Initialization Upon power-up, TriMatrix memory is in an idle state. The M512 and M4K block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. Even if a memory initialization file is used to pre-load the contents of the RAM block, the outputs still power-up cleared.
Page 102: Mixed-Port Read-During-Write Mode
The DONT_CARE setting allows memory implementation in any TriMatrix memory block. The OLD_DATA setting restricts memory implementation to only M512 or M4K memory blocks. Selecting DONT_CARE gives the compiler more flexibility when placing memory functions into TriMatrix memory. 2–26 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 103: Conclusion
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA inclock address A and Address Q address B Port A data_in Port A wren Port B wren Port B data_out For mixed-port read-during-write operation of the same address location...
Page 104 Conclusion 2–28 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 105: Chapter 3. External Memory Interfaces In Stratix & Stratix Gx Devices
(QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT) SRAM, and single data rate (SDR) SDRAM. The dedicated phase-shift circuitry allows the Stratix and Stratix GX devices to interface at twice the system clock speed with an external memory (up to 200 MHz/400 Mbps).
Page 106 DQ pins in ×8 mode. Similarly if your ×32 memory device uses four DQS pins where each DQS pin is associated with eight DQ pins, you need to configure the Stratix and Stratix GX FPGA to use four sets of pins in ×8 mode.
Page 107 Read & Write Operations When reading from the DDR SDRAM, the DQS signal coming into the Stratix and Stratix GX device is edge-aligned with the DQ pins. The dedicated circuitry center-aligns the DQS signal with respect to the DQ signals and the shifted DQS bus drives the clock input of the DDR input registers.
Page 108: Rldram Ii
DQS pin by either 72° or 90° and clocks the DDR input registers. Because of the DDR input registers architecture in Stratix and Stratix GX devices, the shifted DQS signal must be inverted. The DDR registers outputs are sent to two LE registers to be synchronized with the system clock.
Page 109 Stratix GX device DQ pins. If the data pins are uni-directional, connect the RLDRAM II device Q ports to the Stratix and Stratix GX device DQ pins and connect the D ports to any user I/O pins in I/O banks 3, 4, 7, and 8.
Page 110: Qdr & Qdrii Sram
Cn are the inverse of the K and C clocks, respectively. You can use differential HSTL I/O pins to drive the QDR SRAM clock into the Stratix and Stratix GX devices. The separate write data and read data ports permit a transfer rate up to four words on every cycle through the DDR circuitry.
Page 111 K clock's rising edge. You can use any of the Stratix and Stratix GX device user I/O pins in I/O banks 3, 4, 7, and 8 for the D write data ports, commands, and addresses.
Page 112: Zbt Sram
External Memory Standards clock mode, or K or Kn in single clock mode. The edge-aligned CQ and CQn clocks accompany the read data for data capture in Stratix and Stratix GX devices. Figure 3–5. Data & Clock Relationship During a QDRII SRAM Read...
Page 113 The data bus, DQ, is bidirectional. There are three control signals to the ZBT SRAM: RW_N, BW_N, and ADV_LD_N. You can use any of the Stratix and Stratix GX device user I/O pins to interface to the ZBT SRAM device.
Page 114: Ddr Memory Support Overview
For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode.
Page 115: Ddr Memory Interface Pins
DDR SDRAM is supported on the side banks (I/O banks 1, 2, 5, and 6) with no dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices.
Page 116 DDR Memory Support Overview Figure 3–7 shows the DQ and DQS pins in ×8 mode. Figure 3–7. Stratix & Stratix GX Device DQ & DQS Groups in × 8 Mode Top or Bottom I/O Bank DQ Pins (1) DQS Pin...
Page 117 3–3: For V guidelines, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2 or the Stratix GX Handbook, Volume 2. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
Page 118 DDR Memory Support Overview The DQS pins are marked in the Stratix and Stratix GX device pin table as DQS[9..0]T or DQS[9..0]B, where T stands for top and B for bottom. The corresponding DQ pins are marked as DQ[9..0]T[7..0], where [9..0] indicates which DQS group the pins belong to.
Page 119: Dqs Phase-Shift Circuitry
Other Pins (Parity, DM, ECC & QVLD Pins) You can use any of the DQ pins for the parity pins in Stratix and Stratix GX devices. However, this may mean that you are using the next larger DQS/DQ mode. For example, if you need a parity bit for each byte of data, you are actually going to have nine DQ pins per DQS pin.
Page 120 DQS signal. Refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix Device Handbook for frequency limits regarding the 72 and 90° phase shift for DQS. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device.
Page 121 3–8: There are up to 10 DQS and DQSn pins available on the top or the bottom of the Stratix and Stratix GX devices. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device.
Page 122 3–9). The DQS phase-shift circuitry then uses the clock period to generate the correct phase shift. The DLL in the Stratix and Stratix GX devices DQS phase- shift circuitry can operate between 100 and 200 MHz. The phase-shift circuitry needs a maximum of 256 clock cycles to calculate the correct phase shift.
Page 123 DQ IOE registers. For more information, the DQS Postamble soft logic is described in AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. The ® Altera DDR SDRAM controller MegaCore generates this logic as open-source code.
Page 124: Ddr Registers
DDR Memory Support Overview DDR Registers Each Stratix and Stratix GX IOE contains six registers and one latch. Two registers and a latch are used for input, two registers are used for output, and two registers are used for output enable control. The second output enable register provides the write preamble for the DQS strobe in the DDR external memory interfaces.
Page 125 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–10. Bidirectional DDR I/O Path in Stratix & Stratix GX Devices Note (1) OE Register A OE Register B datain_l I/O Pin (7) Output Register A Logic Array datain_h Output Register B...
Page 126 Quartus II software implements this signal as an active high and automatically adds an inverter before the A register D input. Figures 3–12 3–13 summarize the IOE registers used for the DQ and DQS signals. 3–22 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 127 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE Note (1) OE Register A datain_l DQ Pin Output Register A Logic Array datain_h Output Register B outclock (3) dataout_h Input Register A...
Page 128 DDR Memory Support Overview Figure 3–13. DQS Configuration in Stratix & Stratix GX IOE Note (1) OE Register A OE Register B Logic Array datain_h (3) DQS Pin (5) Output Register A datain_l (4) Output Register B system clock undelayed DQS (6)
Page 129 External Memory Interfaces in Stratix & Stratix GX Devices The Stratix and Stratix GX DDR IOE structure requires you to invert the incoming DQS signal by using a NOT gate to ensure proper data transfer. The altdq megafunction automatically adds the inverter when it generates the DQ signals.
Page 130 DQS inverted and shifted by 90˚ Output of register A n − 2 (dataout_h) Output of register B n − 1 Output of latch C n − 3 n − 1 (dataout_l) 3–26 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 131: Pll
The write clock is –90° shifted from the system clock and generates the DQ signals during writes. When using the Stratix and Stratix GX side I/O banks 1, 2, 5, or 6 to interface with DDR SDRAM devices, two PLLs may be needed per I/O bank for best performance.
Page 132 Conclusion 3–28 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 133: Section Iii. I/O Standards
I/O standards. It contains the following chapters: ■ Chapter 4, Selectable I/O Standards in Stratix & Stratix GX Devices ■ Chapter 5, High-Speed Differential I/O Interfaces in Stratix Devices Revision History The table below shows the revision history for Chapters 4 and 5.
Page 134 I/O Standards Stratix Device Handbook, Volume 2 Chapter Date/Version Changes Made Comments September 2004, ● Table 4–1 on page 4–1: renamed table, updated table, and v3.1 added Note 1. ● Deleted Figure named “1.5-V Differential HSTL Class II Termination.” ●...
Page 135 Updated high-speed I/O specification for J=2 in Tables 5-7 and 5-8. ● Updated Tables 5-10 to 5-14 to reflect PLL cross-bank support for high-speed differential channels at full speed. Increased maximum output clock frequency to 462 to 500 ● MHz on page 5-66. Altera Corporation Section III–3...
Page 136 I/O Standards Stratix Device Handbook, Volume 2 Section III–4 Altera Corporation...
Page 137: Introduction
Stratix & Stratix Stratix and Stratix GX devices support a wide range of industry I/O standards as shown in the Stratix Device Family Data Sheet section in the GX I/O Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 138: V Low Voltage Transistor-Transistor Logic (Lvttl) - Eia/Jedec Standard Jesd8-B
These performance values are dependent on device speed grade, package type (flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1. 3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) - EIA/JEDEC Standard JESD8-B The 3.3-V LVTTL I/O standard is a general-purpose, single-ended...
Page 139: 3.3-V Lvcmos - Eia/Jedec Standard Jesd8-B
The 3.3-V I/O standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels for 3.3-V LVCMOS operation. 2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 The 2.5-V I/O standard is used for 2.5-V LVTTL applications.
Page 140: V Lvttl Normal Voltage Range - Eia/Jedec Standard Eia/Jesd8-7
Stratix & Stratix GX I/O Standards Stratix and Stratix GX devices support both input and output levels for 2.5-V LVCMOS operation. 1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This...
Page 141: V Hstl Class I & Ii - Eia/Jedec Standard Eia/Jesd8-6
Selectable I/O Standards in Stratix & Stratix GX Devices Stratix and Stratix GX devices support both input and output levels for 1.5-V LVCMOS operation. 1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6 The high-speed transceiver logic (HSTL) I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic switching...
Page 142: V Differential Hstl - Eia/Jedec Standard Eia/Jesd8-6
50 Ω resistor termination resistor to V at the input buffer (see Figure 4–3). Stratix and Stratix GX devices support both input and output clock levels for 1.5-V differential HSTL. The input clock is implemented using dedicated differential input buffer. Two single-ended output buffers are automatically programmed to have opposite polarity so as to implement a differential output clock.
Page 143: V Pci-X 1.0 Local Bus - Pci-Sig Pci-X Local Bus Specification Revision 1.0A
3.3-V PCI-X Specification Revision 1.0a and meet the 133-MHz operating frequency and timing requirements. The 3.3-V PCI standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels.
Page 144: V 2× Agp - Intel Corporation Accelerated Graphics Port Interface Specification 2.0
The GTL standard defines the DC interface parameters for digital circuits operating from power supplies of 2.5, 3.3, and 5.0 V. The GTL standard is an open-drain standard, and Stratix and Stratix GX devices support a 2.5- or 3.3-V V to meet this standard.
Page 145: Ctt - Eia/Jedec Standard Jesd8-4
Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–5. GTL+ Termination = 1.5 V = 1.5 V Output Buffer 50 Ω 50 Ω Input Buffer Z = 50 Ω = 1.0 V CTT - EIA/JEDEC Standard JESD8-4 The CTT I/O standard is used for backplanes and memory bus interfaces.
Page 146: Sstl-2 Class I & Ii - Eia/Jedec Standard Jesd8-9A
1.25-V CCIO to which the series and termination resistors are connected (see Figures 4–9 and 4–10). Stratix and Stratix GX devices support both input and output levels. Figure 4–9. SSTL-2 Class I Termination = 1.25 V Output Buffer 50 Ω...
Page 147: Sstl-18 Class I & Ii - Eia/Jedec Preliminary Standard Jc42.3
See Figures 4–11 4–12 for details on SSTL-18 Class I and II termination. Stratix and Stratix GX devices support both input and output levels. Figure 4–11. SSTL-18 Class I Termination = 0.9 V Output Buffer 50 Ω...
Page 148: Lvds - Ansi/Tia/Eia Standard Ansi/Tia/Eia-644
655 Mbps. However, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX devices meet the ANSI/TIA/EIA-644 standard. Due to the low voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than CMOS, TTL, and PECL.
Page 149: Lvpecl
Selectable I/O Standards in Stratix & Stratix GX Devices For more information on the LVDS I/O standard in Stratix devices, see the High-Speed Differential I/O Interfaces in Stratix Devices chapter. LVPECL The LVPECL I/O standard is a differential interface standard requiring a 3.3-V V...
Page 150: Hypertransport Technology - Hypertransport Consortium
Figure 4–16 for details on PCML termination. Stratix and Stratix GX devices support both input and output levels. Additionally, Stratix GX devices support 1.5-V PCML as described in the Stratix GX Device Handbook, Volume 1. Figure 4–16. PCML Termination Output Buffer 50 Ω...
Page 151: High-Speed Interfaces
Selectable I/O Standards in Stratix & Stratix GX Devices See the Stratix Device Family Data Sheet section in the Stratix Device Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O Interfaces in Stratix Devices chapter for more information on differential I/O standards.
Page 152: Gigabit Ethernet Sixteen Bit Interface (Xsbi) - Ieee Draft Standard P802.3Ae/D2.0
The RapidIO standard provides 10-Gbps device bandwidth using 8-bit-wide input and output data ports. RapidIO uses LVDS technology, has the capability to be scaled to multi-GHz frequencies, and features a 10-bit interface. 4–16 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 153: Hypertransport Technology - Hypertransport Consortium
ATM cells. UTOPIA Level 4 also supports interconnections across motherboards, daughtercards, and backplane interfaces. Stratix & Stratix Stratix devices have eight I/O banks in addition to the four enhanced PLL external clock output banks, as shown in Table 4–2 Figure 4–18.
Page 154 Since Stratix devices support both non-voltage-referenced and voltage-referenced I/O standards, there are different guidelines when working with either separately or when working with both. Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 1 of 2) Enhanced PLL External I/O Bank...
Page 155 Selectable I/O Standards in Stratix & Stratix GX Devices Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 2 of 2) Enhanced PLL External I/O Bank Clock Output Banks I/O Standard GTL+ LVDS HyperTransport technology LVPECL PCML Notes to Table 4–2:...
Page 156 Stratix & Stratix GX I/O Banks Figure 4–18. Stratix I/O Banks Notes (1), (2), DQS9T DQS8T DQS7T DQS6T DQS5T DQS4T DQS3T DQS2T DQS1T DQS0T PLL5 PLL11 PLL7 VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10 Bank 3 Bank 4 LVDS, LVPECL, 3.3-V PCML,...
Page 157 I/O standards that Stratix GX enhanced and fast PLL pins support. Figure 4–19 shows the I/O standards that each Stratix GX I/O bank supports. Table 4–3. I/O Standards Supported in Stratix & Stratix GX Enhanced PLL Pins Input Output I/O Standard INCLK...
Page 158 Stratix & Stratix GX I/O Banks Table 4–4. I/O Standards Supported in Stratix & Stratix GX Fast PLL Pins Input I/O Standard INCLK PLLENABLE LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML...
Page 159 I/O Bank 1 I/O Bank 5 I/O Bank 5 Contains Transceiver Blocks There is some flexibility with the number of I/O standards each Stratix I/O bank can simultaneously support. The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in Stratix devices.
Page 160: Non-Voltage-Referenced Standards
Non-Voltage-Referenced Standards Each Stratix I/O bank has its own VCCIO pins and supports only one , either 1.5, 1.8, 2.5 or 3.3 V. A Stratix I/O bank can simultaneously CCIO support any number of input signals with different I/O standard...
Page 161: Mixing Voltage Referenced & Non-Voltage Referenced Standards
Selectable I/O Standards in Stratix & Stratix GX Devices An I/O bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same V setting. For example, although one I/O bank can implement both SSTL-3 and SSTL-2 I/O standards, I/O pins using these...
Page 162: Standard Current Drive Strength
Drive Strength Drive Strength Each I/O standard supported by Stratix and Stratix GX devices drives out a minimum drive strength. When an I/O is configured as LVTTL or LVCMOS I/O standards, you can specify the current drive strength, as summarized in Table 4–7.
Page 163: Programmable Current Drive Strength
For mixed-voltage environments, you can drive signals into the device before or during power-up or power-down without damaging the device. Stratix and Stratix GX devices do not drive out until the device is configured and has attained proper operating conditions.
Page 164: Dc Hot Socketing Specification
Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices white paper. I/O Termination Although single-ended, non-voltage-referenced I/O standards do not require termination, Altera recommends using external termination to improve signal integrity where required. The following I/O standards do not require termination: ■...
Page 165: Differential I/O Standards
Selectable I/O Standards in Stratix & Stratix GX Devices For more information on termination for voltage-referenced I/O standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device Handbook, Volume 2. Differential I/O Standards Differential I/O standards typically require a termination resistor between the two signals at the receiver.
Page 166: Transceiver Termination
I/O Pad Placement Guidelines Differential termination for Stratix devices is supported for the left and right I/O banks. Differential termination for Stratix GX devices is supported for the left, source-synchronous I/O bank. Some of the clock input pins are in the top and bottom I/O banks, which do not support differential termination.
Page 167: Vref Pad Placement Guidelines
Selectable I/O Standards in Stratix & Stratix GX Devices ■ For flip-chip packages, there are no restrictions for placement of single-ended input signals with respect to differential signals (see Figure 4–21). For wire-bond packages, single ended input pads may only be placed four or more pads away from a differential pad.
Page 168 See the following equation. <Total number of bidirectional pads> + <Total number of input pads> ≤ 40 (20 on each side of the VREF pad) 4–32 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 169 Selectable I/O Standards in Stratix & Stratix GX Devices The previous equation accounts for the input limitations, but you must apply the appropriate equation from Table 4–9 to determine the output limitations. Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Page 170: Output Enable Group Logic Option In Quartus Ii
You can enable the logic options through the Assignment Editor or by adding the following assignments to your project’s ESF file: OPTIONS_FOR_INDIVIDUAL_NODES_ONLY dq : OUTPUT_ENABLE_GROUP 1; dqs : OUTPUT_ENABLE_GROUP 1; 4–34 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 171: Toggle Rate Logic Option In Quartus Ii
The Quartus II software automatically takes these variables into account during compilation. For any 10 consecutive output pads in an I/O bank, Altera recommends a maximum current of 200 mA for thermally enhanced FineLine BGA and thermally enhanced BGA cavity up packages and 164 mA for non-thermally enhanced cavity up and non-thermally enhanced FineLine BGA packages.
Page 172 4–12: The current rating on a V pin is less than 10μA. For more information on Altera device packaging, see the Package Information for Stratix Devices chapter in the Stratix Device Handbook, Volume 2. 4–36 Altera Corporation Stratix Device Handbook, Volume 2...
Page 173 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–22. Current Draw Limitation Guidelines I/O Pin Sequence of an I/O Bank Any 10 Consecutive I/O Pins, Any 10 consecutive I/O pads cannot exceed 200 mA in thermally enhanced FineLine BGA and thermally enhanced BGA cavity up packages or 164 mA in non-thermally enhanced cavity up and non- thermally enhanced FineLine BGA packages.
Page 174: Power Source Of Various I/O Standards
Power Source of Various I/O Standards Power Source of For Stratix and Stratix GX devices, the I/O standards are powered by different power sources. To determine which source powers the input Various I/O buffers, see Table 4–13. All output buffers are powered by V...
Page 175: Device & Pin Options
Selectable I/O Standards in Stratix & Stratix GX Devices Device & Pin Options Click Device & Pin Options in the Compiler Settings dialog box to access the I/O pin settings. For example, in the Voltage tab you can select a default I/O standard for all pins for the targeted device. I/O pins that do not have a specific I/O standard assignment default this standard.
Page 176: Programmable Drive Strength Settings
Quartus II software color codes the I/O bank to which each I/O pin and pin belong. Turn on the Show I/O Banks option to display the I/O CCIO bank color and the bank numbers for each pin. 4–40 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 177: Auto Placement & Verification Of Selectable I/O Standards
Verifies that voltage-referenced I/O pins requiring different V levels are not placed in the same bank. ■ Reports an error message if the current limit is exceeded for a Stratix or Stratix GX power bank, as determined by the equation documented in “DC Guidelines”...
Page 178: Conclusion
Conclusion Conclusion Stratix and Stratix GX devices provide the I/O capabilities to allow you to work with current and emerging I/O standards and requirements. Today’s complex designs demand increased flexibility to work with the wide variety of available I/O standards and to simplify board design.
Page 179 Selectable I/O Standards in Stratix & Stratix GX Devices ■ Accelerated Graphics Port Interface Specification 2.0, Intel Corporation. ■ Stub Series Terminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3, Electronic Industries Association. ■ PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 1998.
Page 180 References 4–44 Altera Corporation Stratix Device Handbook, Volume 2 June 2006...
Page 181: Chapter 5. High-Speed Differential I/O Interfaces In Stratix Devices
I/O interfaces which have dedicated serializer/deserializer (SERDES) circuitry for each differential I/O pair. Stratix SERDES circuitry transmits and receives up to 840 megabits per second (Mbps) per channel. The differential I/O interfaces in Stratix devices support many high-speed I/O standards, such as LVDS, LVPECL, PCML, and HyperTransport technology.
Page 182: Stratix Differential I/O Standards
Figure 5–1: Figure 5–1 is a top view of the Stratix silicon die, which corresponds to a top-down view of non-flip-chip packages and a bottom-up view of flip-chip packages. Figure 5–1 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
Page 183 High-Speed Differential I/O Interfaces in Stratix Devices SSTL-2 Class I and II. This feature makes the Stratix device family ideal for applications that require multiple I/O standards, such as a protocol translator. For more information on termination for Stratix I/O standards, see “Differential I/O Termination”...
Page 184 I/O standard is a point-to-point standard in which each HyperTransport technology bus consists of two point-to-point unidirectional links. Each link is 2 to 32 bits. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the HyperTransport parameters.
Page 185: Stratix Differential I/O Pin Location
CCIO and output levels. The differential SSTL-2 I/O standard is only available on output clocks. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics. Stratix Differential I/O Pin Location The differential I/O pins are located on the I/O banks on the right and left side of the Stratix device.
Page 186: Principles Of Serdes Operation
I/O standards. DDRIO capabilities are detailed in “SERDES Bypass DDR Differential Signaling” page 5–42. Table 5–1. I/O Pin Locations on Each Side of Stratix Devices Device Side Differential Input Differential Output DDRIO Left...
Page 187: Stratix Differential I/O Receiver Operation
High-Speed Differential I/O Interfaces in Stratix Devices Stratix Differential I/O Receiver Operation You can configure any of the Stratix differential input channels as a receiver channel (see Figure 5–3). The differential receiver deserializes the incoming high-speed data. The input shift register continuously clocks the incoming data on the negative transition of the high-frequency ×...
Page 188 Principles of SERDES Operation × Figure 5–3. Stratix High-Speed Interface Deserialized in 10 Mode Receiver Circuit Serial Shift Parallel Parallel Registers Registers Registers RXIN+ RXIN− Stratix Logic Array × W × W / J (1) RXCLKIN+ Fast RXLOADEN RXCLKIN− PLL (2)
Page 189: Stratix Differential I/O Transmitter Operation
High-Speed Differential I/O Interfaces in Stratix Devices Stratix Differential I/O Transmitter Operation You can configure any of the Stratix differential output channels as a transmitter channel. The differential transmitter is used to serialize outbound parallel data. The logic array sends parallel data to the SERDES transmitter circuit when the TXLOADEN signal is asserted.
Page 190: Transmitter Clock Output
20KE and APEX II devices, Stratix ® devices do not have a fixed transmitter clock output pin. The Altera Quartus II software generates the transmitter clock output by using a fast clock to drive a transmitter dataout channel. Therefore, you can place the transmitter clock pair close to the data channels, reducing clock-to- data skew and increasing system margins.
Page 191: Center-Aligned Transmitter Clock Output
High-Speed Differential I/O Interfaces in Stratix Devices Table 5–2 shows the divided-down version of the high-frequency clock and the selected serialization factor J (described in pervious sections). The Quartus II software automatically generates the data input to the additional transmitter data channel.
Page 192: Sdr Transmitter Clock Output
You can route the high-frequency clock internally generated by the PLL out as a transmitter clock output on any of the differential channels. The high-frequency clock output allows Stratix devices to support applications that require a 1-to-1 relationship between the clock and data.
Page 193: Using Serdes To Implement Ddr
Rapid I/O, SPI-4 Phase 2 (POS_PHY Level 4), or to Implement HyperTransport interfaces, and support various data rates. Stratix devices meet this requirement for such applications by providing a variable clock division factor. The SERDES clock division factor is set to 2 for double data rate (DDR).
Page 194: Using Serdes To Implement Sdr
× W LVDS PLL txclk_in 100 MHz Using SERDES Stratix devices support systems based on single data rate (SDR) operations applications by allowing you to directly transmit out the to Implement multiplied clock (as described in “SDR Transmitter Clock Output” on page 5–12).
Page 195 High-Speed Differential I/O Interfaces in Stratix Devices automatically assigns a seventeenth channel as the transmitter clock output. You can edge- or center-align the transmitter clock output by selecting the default PLL phase or selecting the 90° phase of the PLL output.
Page 196: Differential I/O Interface & Fast Plls
PLLs support all I/O standards or from enhanced and fast PLL outputs. Stratix devices use the fast PLLs to implement clock multiplication and division to support the SERDES circuitry. The input clock is either multiplied by the W feedback factor and/or divided by the J factor. The resulting clocks are distributed to SERDES, local, or global clock lines.
Page 197 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–13. Stratix Fast PLL Positions & Clock Naming Convention Note (1) CLK[15..12] FPLLCLK0 FPLLCLK3 CLK[3..0] CLK[11..8] PLLs FPLLCLK1 FPLLCLK2 CLK[7..4] Notes to Figure 5–13: Dedicated clock input pins on the right and left sides do not support PCI or PCI-X 1.0.
Page 198: Clock Input & Fast Pll Output Relationship
PLL interface to the input clocks and the enable signal (ENA). Table 5–4 summarizes the clock networks each fast PLL can connect to across all Stratix family devices. Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables Note (1) All Stratix Devices...
Page 199 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 1 of 2) Notes (1), All Stratix Devices EP1S30 to EP1S80 Devices Only Output Signal PLL 1 PLL 2 PLL 3 PLL 4...
Page 200: Fast Pll Specifications
Differential I/O Interface & Fast PLLs Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2) Notes (1), All Stratix Devices EP1S30 to EP1S80 Devices Only Output Signal PLL 1 PLL 2 PLL 3 PLL 4 PLL 7...
Page 201: High-Speed Phase Adjust
Notes to Figure 5–14: In high-speed differential I/O mode, the high-speed PLL clock feeds the SERDES. Stratix devices only support one rate of data transfer per fast PLL in high-speed differential I/O mode. Control signal for high-speed differential I/O SERDES.
Page 202: Counter Circuitry
÷ l Regional clock clkin The Stratix device fast PLL has another GCLK connection for general- purpose applications. The third tap l feeds the quadrant local clock as well as the global clock network. You can use the l counter's multiplexer for applications requiring the device to connect the incoming clock directly to the local or global clocks.
Page 203: Fast Pll Serdes Channel Support
High-Speed Differential I/O Interfaces in Stratix Devices Fast PLL SERDES Channel Support The Quartus II MegaWizard Plug-In Manager only allows you to implement up to 20 receiver or 20 transmitter channels for each fast PLL. These channels operate at up to 840 Mbps. For more information on implementing more than 20 channels, see “Fast PLLs”...
Page 204 There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps. 5–24 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 205: Advanced Clear & Enable Control
The reset signals are reset/resynchronization inputs for each enhanced PLL. Stratix devices can drive these input signals from an input pin or from LEs. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. When driven low again, the PLL resynchronizes to its input as it relocks.
Page 206 SERDES circuitry (shown in Figure 5–3 on page 5–8). Figure 5–18 shows the function-timing diagram of a Stratix SERDES in × normal 8 mode, and Figure 5–19 shows the function-timing diagrams of a Stratix SERDES when data realignment is used.
Page 207: Generating The Txloaden Signal
High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–19. SERDES Function Timing Diagram with Data-Realignment Operation ×8 clock Serial data ×1 clock Generating the TXLOADEN Signal The TXLOADEN signal controls the transfer of data between the SERDES circuitry and the logic array when data realignment is used. To prevent the interruption of the TXLOADEN signal during data realignment, both k and v counter are used.
Page 208: Realignment Implementation
RXLOADEN signal is delayed by one high-frequency clock period and the parallel bits shift by one bit. Figure 5–21 shows the timing relationship between the high-frequency clock, the RXLOADEN signal, and the parallel data. 5–28 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 209 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–21. Realignment by rx_data_align Node End 10× clock 1× clock SYNC rxloaden datain receiver A 0123456789 0123456789 1234567890 1234567890 receiver B A state machine can generate the realignment signal to control the alignment procedure.
Page 210: Source-Synchronous Timing Budget
This section defines the source- synchronous differential data orientation timing parameters, and timing budget definitions for Stratix devices, and explains how to use these timing parameters to determine a design's maximum performance. Differential Data Orientation There is a set relationship between an external clock and the incoming data.
Page 211: Differential I/O Bit Position
High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–23. Bit Orientation in the Quartus II Software inclock/outclock 10 LVDS Bits data in high-frequency clock Differential I/O Bit Position Data synchronization is necessary for successful data transmission at high frequencies. Figure 5–24 shows the data bit orientation for a receiver ×...
Page 212: Timing Definition
Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2) High-Speed Timing Specification Terminology High-speed receiver/transmitter input and output clock period. High-speed receiver/transmitter input and output clock frequency. HSCLK Low-to-high transmission time. RISE 5–32 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 213 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2) High-Speed Timing Specification Terminology High-to-low transmission time. FALL Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window.
Page 214 Tables 5–7 5–8 show the high-speed I/O timing for Stratix devices Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3) Notes (1), -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Conditions Unit...
Page 215 Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 3) Notes (1), -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Conditions Unit Device J = 10 Mbps HSDR operation (PCML) J = 8 Mbps J = 7 Mbps...
Page 216 Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3) Notes (1), -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Conditions Unit Output t LVDS FALL HyperTransport technology LVPECL PCML LVDS (J = 2 through 47.5 52.5 47.5...
Page 217 Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 3) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Conditions Unit Device operation, J = 10 Mbps HSDR (LVDS,LVPECL, HyperTransport J = 8 Mbps technology) J = 7 Mbps J = 4 Mbps...
Page 218 Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 3 of 3) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Conditions Unit Input jitter tolerance (peak-to- peak) Output jitter (peak-to-peak) Output t LVDS R I S E HyperTransport technology LVPECL PCML Output t...
Page 219: Input Timing Waveform
High-Speed Differential I/O Interfaces in Stratix Devices Input Timing Waveform Figure 5–25 illustrates the essential operations and the timing relationship between the clock cycle and the incoming serial data. For a functional description of the SERDES, see “Principles of SERDES Operation”...
Page 220: Output Timing
The timing margin between receiver’s clock input and the data input sampling window is known as RSKM. Figure 5–27 illustrates the relationship between the parameter and the receiver’s sampling window. 5–40 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 221 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget Timing Diagram External Input Clock Time Unit Interval (TUI) Internal Clock TCCS TCCS Sampling Receiver RSKM RSKM Window (SW) Input Clock TPPos (max) TPPos (max)
Page 222: Switching Characteristics
For static timing analysis, the timing characteristics of the differential I/O standards are guaranteed by design and depend on the frequency at which they are operated. Use the values in the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 to calculate system timing margins for various I/O protocols.
Page 223: Serdes Bypass Ddr Differential Signaling Receiver Operation
High-Speed Differential I/O Interfaces in Stratix Devices SERDES Bypass DDR Differential Signaling Receiver Operation The SERDES bypass differential signaling receiver uses the Stratix device DDR input circuitry to receive high-speed serial data. The DDR input circuitry consists of a pair of shift registers used to capture the high-speed serial data, and a latch.
Page 224: Serdes Bypass Ddr Differential Signaling Transmitter Operation
SERDES Bypass DDR Differential Signaling Transmitter Operation × 2 differential signaling transmitter uses the Stratix device DDR output circuitry to transmit high-speed serial data. The DDR output circuitry consists of a pair of shift registers and a multiplexer. The shift registers capture the parallel data on the clock’s rising edge (generated by...
Page 225: High-Speed Interface Pin Locations
×1 ×4 ×1 inclock High-Speed Stratix high-speed interface pins are located at the edge of the package to limit the possible mismatch between a pair of high-speed signals. Stratix Interface Pin devices have eight programmable I/O banks. Figure 5–32 shows the I/O pins and their location relative to the package.
Page 226: Differential I/O Termination
Figure 5–33 shows the device with differential termination for the LVDS I/O standard. For more information on differential on-chip termination technology, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter. 5–46 Altera Corporation Stratix Device Handbook, Volume 2...
Page 227: Hypertransport & Lvpecl Differential Termination
High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–33. LVDS Differential On-Chip Termination LVDS Receiver with LVDS Transmitter On-Chip 100-Ω Termination = 50 Ω = 50 Ω HyperTransport & LVPECL Differential Termination HyperTransport and LVPECL I/O standards are terminated by an external 100-Ω...
Page 228: Differential Hstl Termination
HSTL Class I and II I/O standard. Figure 5–36. Differential HSTL Class I Termination = 0.75 V = 0.75 V Differential Differential 50 Ω 50 Ω Transmitter Receiver = 50 Ω = 50 Ω 5–48 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 229: Differential Sstl-2 Termination
High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–37. Differential HSTL Class II Termination = 0.75 V = 0.75 V = 0.75 V = 0.75 V Differential Differential 50 Ω 50 Ω 50 Ω 50 Ω Transmitter Receiver = 50 Ω...
Page 230: Board Design Consideration
IC. For more information, use this chapter and the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. The Stratix high-speed module generates signals that travel over the media at frequencies as high as 840 Mbps.
Page 231: Software Support
RAM blocks closest to the differential pins for deserialization in SERDES bypass mode. Differential Pins in Stratix Stratix device differential pins are located in I/O banks 1, 2, 5, and 6 (see Figure 5–1 on page 5–2). Each bank has differential transmitter and differential receiver pin pairs.
Page 232: Fast Plls
Software Support Stratix devices can drive the PLL_LOCK signal to both output pins and internal logic. As a result, you do not need a dedicated LOCK pin for your PLLs. In addition, there is only one PLL_ENABLE pin that enables all the PLLs on the device, including the fast PLLs.
Page 233 Quartus II software. The Quartus II software gives an error message if you try to compile a design exceeding the maximum number of channels. Additional high-speed DIFFIO pin information for Stratix devices is available in Volume 3 of the Stratix Device Handbook.
Page 234 672-pin FineLine BGA Transmitter 672-pin BGA Receiver 780-pin FineLine BGA Transmitter Receiver EP1S20 484-pin FineLine BGA Transmitter Receiver 672-pin FineLine BGA Transmitter 672-pin BGA Receiver 780-pin FineLine BGA Transmitter Receiver 5–54 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 235 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1) Maximum Center Fast PLLs Transmitter/ Total Device Package Speed Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4...
Page 236 Center Fast PLLs Corner Fast PLLs (2), Transmitter Total Package Speed /Receiver Channels PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 780-pin Transmitter FineLine Receiver 956-pin Transmitter FineLine Receiver 5–56 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 237 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–12. EP1S40 Differential Channels (Part 2 of 2) Note (1) Maximum Center Fast PLLs Corner Fast PLLs (2), Transmitter Total Package Speed /Receiver Channels PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10...
Page 238 PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 956-pin Transmitter 80 (40) FineLine Receiver 1,020-pin Transmitter 80 (12) FineLine Receiver 80 (10) 10 (3) 10 (2) 10 (3) 10 (2) 5–58 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 239 For the location of these channels, see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com). See device pin-outs channels marked “high” speed are 840 Mbps and “low” speed channels are 462 MBps.
Page 240: Lvds Receiver Block
Only one rx_pll_enable pin is necessary to enable all the PLLs in the device. This is a non-differential pin. “Realignment Implementation” on page 5–28 for more information. For guaranteed performance and data alignment, you must synchronize rx_data_align with rx_outclock. 5–60 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 241 High-Speed Differential I/O Interfaces in Stratix Devices Use the altlvds MegaWizard Plug-In Manager to create an LVDS receiver block. The following sections explain the parameters available in the Plug-In Manager when creating an LVDS receiver block. Page 3 of the altlvds_rx MegaWizard Plug-In Manager On page 3 of the altlvds MegaWizard Plug-In Manager, you can choose to create either an LVDS transmitter or receiver.
Page 242 This parameter’s value must be larger than the input clock frequency and has a maximum input data rate of 840 Mbps for Stratix devices. You do not have to provide a value for the inclock boost (W) when designing with Stratix devices because the Quartus II software can calculate it automatically from this parameter and the clock frequency or clock period.
Page 243 High-Speed Differential I/O Interfaces in Stratix Devices Clock Frequency or Clock Period The fields in the Specify the input clock rate by box specify the input frequency or the period of the input clock going into the fast PLL. When...
Page 244 LVDS receiver. You need to assert the port for at least two clock cycles to enable the data realignment circuitry. Go to the Altera web site at www.altera.com for a sample design written in Verilog HDL.
Page 245: Lvds Transmitter Module
High-Speed Differential I/O Interfaces in Stratix Devices LVDS Transmitter Module The Quartus II software calculates the inclock boost (W) factor for the LVDS transmitter based on input data rate, input clock frequency, and the deserialization factor. In addition to setting the data and clock...
Page 246 MSB (rx_out bit × × n) – 1]) to the LSB (rx_out bit [J (n – 1)]), where J is the 5–66 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 247 PLL and determines the input clock boost/multiplication factor needed for the transmitter. This parameter must be larger than the input clock frequency and has a maximum rate of 840 Mbps for Stratix devices. The input clock boost factor (W) is the output data rate divided by the input clock frequency.
Page 248 Software Support Stratix devices, you can align the input data with respect to the tx_inclock port and align the output data with respect to the tx_outclock port. The MegaWizard Plug-In Manager uses the alignment of input and output data to automatically calculate the phase for the fast PLL outputs.
Page 249 Use Common PLL for Transmitter & Receiver Check the Use Common PLLs for Rx and Tx box to place both the LVDS transmitter and receiver in the same I/O bank in Stratix devices. The Quartus II software also allows the transmitter and receiver to share the PLL when the same input clock is used for both.
Page 250: Serdes Bypass Mode
1 mode, you only need to specify the I/O standard of the pins to tell the Quartus II software that you are using differential signaling. However, Altera recommends using the DDRIO circuitry when the input or output data rate is higher than 231 Mbps. The maximum output clock ×...
Page 251 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–44. LVDS x2 Mode Schematic Using DDR I/O Circuitry DDIO In DDIO Out datain[0] dataout_h[0] datain_h[0] dataout[0] inclock dataout_l[0] datain_l[0] Custom Logic outclock RX_PLL DDIO Out rx_inclk tx_outclk inclock /1 clock1 datain_h[0]...
Page 252 W-UpCounter RX_PLL core_clk ÷1 clock1 inclock ×2 clock0 clock q[5..0] raddr[5..3] RX_PLL tx_outclk datain_h[0] /1 clock1 R-UpCounter datain_l[0] /2 clock0 outclock 5–72 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 253 High-Speed Differential I/O Interfaces in Stratix Devices For the transmitter, the read counter is the fast counter and the write counter is the slow counter. For the receiver, the write counter is the fast counter and the read counter is the slow counter.
Page 254 3, 5, 7] ×4 clock0 Data to Clock DFF[7..0] Input logic array ÷2 clock1 data_l data data[0, 2, 4, 6] Shift Register clock rx_clk 5–74 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 255: Summary
Stratix devices can easily implement processing-intensive data- path functions that are received and transmitted at high speeds. The Stratix family of devices combines a high-performance enhanced PLD architecture with dedicated I/O circuitry in order to provide I/O standard performances of up to 840 Mbps.
Page 256 Summary 5–76 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 257: Section Iv. Digital Signal Processing (Dsp)
(DSP) functions and arithmetic operations in the on- chip DSP blocks. It contains the following chapters: ■ Chapter 6, DSP Blocks in Stratix & Stratix GX Devices ■ Chapter 7, Implementing High Performance DSP Functions in Stratix & Stratix GX Devices...
Page 258 Digital Signal Processing (DSP) Stratix Device Handbook, Volume 2 Section IV–2 Altera Corporation...
Page 259: Chapter 6. Dsp Blocks In Stratix & Stratix Gx Devices
Software Support See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 for more information on Stratix and Stratix GX devices, respectively.
Page 260: Dsp Block Overview
DSP Block Overview DSP Block Each Stratix and Stratix GX device has two columns of DSP blocks that efficiently implement multiplication, multiply accumulate (MAC), and Overview filtering functions. Figure 6–1 shows one of the columns with surrounding LAB rows. You can configure each DSP block to support: Eight 9 ×...
Page 261 Tables 6–1 6–2 describe the number of DSP blocks in each Stratix and Stratix GX device, respectively, and the multipliers that you can implement. Table 6–1. Number of DSP Blocks in Stratix Devices Note (1) 9 × 9 Multipliers 18 ×...
Page 262 Output From the Row Register Interface Block CLRN CLRN CLRN Adder/ Subtractor/ Accumulator CLRN CLRN Summation Block CLRN Adder CLRN CLRN CLRN Adder/ Subtractor/ Accumulator Pipeline Register CLRN CLRN CLRN 6–4 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 263: Architecture
DSP Blocks in Stratix & Stratix GX Devices Architecture The DSP block consists of the following elements: ■ A multiplier block ■ An adder/subtractor/accumulator block ■ A summation block ■ An output interface ■ Output registers ■ Routing and control signals...
Page 264 DSP block. This implementation greatly reduces the required LE count and routing resources, and produces repeatable timing. 6–6 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 265 DSP Blocks in Stratix & Stratix GX Devices Figure 6–4. Shift Register Chain DSP Block 0 Data A A[n] × B[n] CLRN Data B CLRN CLRN shiftoutb shiftouta A[n - 1] × B[n - 1] CLRN CLRN CLRN shiftouta shiftoutb DSP Block 1 A[n - 2] ×...
Page 266 In the DSP block, pipelining improves the performance of 36 × 36 multipliers. For 18 × 18 multipliers and smaller, pipelining adds latency but does not improve performance. 6–8 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 267: Adder/Output Block
DSP Blocks in Stratix & Stratix GX Devices Adder/Output Block The adder/output block has the following elements (See Figure 6–5 on page 6–10): ■ An adder/subtractor/accumulator block ■ A summation block ■ An output select multiplexer ■ Output registers You can configure the adder/output block as: ■...
Page 268 Accumulator When the adder/subtractor/accumulator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in Figure 6–5. You can use the 6–10 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 269 DSP Blocks in Stratix & Stratix GX Devices accum_sload[1..0] signals to clear the accumulator asynchronously. This action is not the same as resetting the output registers. You can clear the accumulation and begin a new one without losing any clock cycles.
Page 270: Routing Structure & Control Signals
18 data signals per row and 18 control signals per block. Output Interface The DSP block output interface drives 144 outputs to adjacent LABs, 18 signals per row from 8 rows. 6–12 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 271 DSP Blocks in Stratix & Stratix GX Devices Because the DSP block outputs communicate horizontally, and because each DSP block row has more outputs than an LAB (18 from the DSP block compared to 10 from an LAB), the DSP block has double the number of row channel drivers compared to an LAB.
Page 272 Each register is grouped in banks that share the same clock and clear resources: ■ 1- to 9-bit banks for the input register ■ 1- to 18-bit banks for the pipeline register ■ 18 bits for the output register 6–14 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 273 DSP Blocks in Stratix & Stratix GX Devices The row interface block generates the control signals and routes them to the DSP block. Each DSP block has 18 control signals: ■ Four clock signals (clock[3..0]), which are available to each bank of DSP blocks ■...
Page 274 Routed from 30 Local Interconnects or LAB Row Clock Four Clock Signals Routed from LAB Row 2 Row Clock or Local Interconnect 18 × 18 Multiplier Row 7 Row 8 6–16 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 275 DSP Blocks in Stratix & Stratix GX Devices Each row block provides 18 bits of data to the multiplier (i.e., one of the operands to the multiplier), which are routed through the 30 local interconnects within each DSP row interface block. Any signal in the device can be the source of the 18-bit multiplier data, by connecting to the local row interconnect through any row or column.
Page 276: Operational Modes
Simple Multiplier Mode In simple multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers and for applications such as equalizer coefficient updates that require many individual multiplication operations. 6–18 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 277 DSP Blocks in Stratix & Stratix GX Devices 9- & 18-Bit Multipliers You can configure each DSP block multiplier for 9 or 18 bits. A single DSP block can support up to 8 individual 9-bit or smaller multipliers, or up to 4 individual multipliers with operand widths between 10- and 18-bits.
Page 278 The 36 × 36-bit multiplier supports signed and unsigned operation. The 36-bit multiplier is useful when your application needs more than 18-bit precision, for example, for mantissa multiplication of precision floating-point arithmetic applications. 6–20 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 279 DSP Blocks in Stratix & Stratix GX Devices Figure 6–11. 36-Bit Multiplier signa signb A[17..0] CLRN CLRN B[17..0] CLRN A[35..18] Data Out Partial CLRN Product CLRN Summation CLRN Block B[35..18] CLRN A[35..18] CLRN CLRN B[17..0] CLRN A[17..0] CLRN CLRN B[35..18]...
Page 280: Multiply Accumulator Mode
The DSP block can then begin a new accumulation without losing any clock cycles. The overflow signal indicates an overflow or underflow in the accumulator. This signal is 6–22 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 281: Two-Multiplier Adder Mode
DSP Blocks in Stratix & Stratix GX Devices cleared for the next accumulation cycle, and you can use an external latch to preserve the signal. You can use the addnsub[1..0] signals to perform accumulation or subtraction dynamically. If you want to use DSP blocks and your design only has an...
Page 282: Four-Multiplier Adder Mode
A single DSP block can implement one 18 × 18 or two 9 × 9 summation blocks (see Figure 6–14 on page 6–25). The multiplier product widths must be the same size. 6–24 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 283 DSP Blocks in Stratix & Stratix GX Devices Figure 6–14. Four-Multiplier Adder Mode signa signb shiftina aclr clock shiftinb Data A CLRN Adder/ Subtractor CLRN Data B CLRN Data A Data Out addnsub0 Adder CLRN signa CLRN signb CLRN addnsub1...
Page 284 One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, you can cascade DSP blocks with additional adder stages implemented in logic elements. 6–26 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 285 DSP Blocks in Stratix & Stratix GX Devices Figure 6–15. Input Shift Registers Configured for a FIR Filter Data A A[n] × B[n] (to adder) CLRN Data B CLRN CLRN Data B Data A A[n - 1] × B[n - 1] (to adder)
Page 286: Software Support
DSP blocks during compilation. See the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device Handbook, Volume 2 for more information on using DSP blocks to implement high-performance DSP functions such as FIR filters, IIR filters, and discreet cosine transforms (DCTs).
Page 287: Chapter 7. Implementing High Performance Dsp Functions
DSP blocks optimized for implementing arithmetic operations, such as multiply, multiply-add, and multiply-accumulate. In addition to DSP blocks, Stratix and Stratix GX devices have TriMatrix™ embedded memory blocks that feature various sizes that can be used for data buffering, which is important for most DSP applications.
Page 288 Stratix & Stratix GX DSP Block Overview Figure 7–1. DSP Block Diagram for 18 x 18-bit Mode Optional Serial Shift Register Inputs from Previous DSP Block Multiplier Stage Optional Stage Configurable Output Selection as Accumulator or Dynamic Multiplexer Adder/Subtractor CLRN...
Page 289 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices The DSP blocks are organized into columns enabling efficient horizontal communication with adjacent TriMatrix memory blocks. Tables 7–1 7–2 show the DSP block resources in Stratix and Stratix GX devices, respectively.
Page 290: Trimatrix Memory Overview
DSP block to allow pipelining. For implementing applications, such as FIR filters, efficiently use the input registers of the DSP block as shift registers. For more information on DSP blocks, see the DSP Blocks in Stratix & Stratix GX Devices chapter. TriMatrix Stratix and Stratix GX devices feature the TriMatrix memory structure, composed of three sizes of embedded RAM blocks.
Page 291: Dsp Function Overview
The following sections describe commonly used DSP functions. Each section illustrates the implementation of a basic DSP building block, Overview including FIR and IIR filters, in Stratix and Stratix GX devices using DSP blocks and TriMatrix memory blocks. Finite Impulse...
Page 292: Fir Filter Background
The width of the output bus depends on the number of taps and the bit width of the input and coefficients. 7–6 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 293: Basic Fir Filter
For implementing FIR filters, the DSP blocks are configured in the four-multipliers adder mode. See the DSP Blocks in Stratix & Stratix GX Devices chapter for more information on the different modes of the DSP blocks. This section describes the implementation of an 18-bit 8-tap FIR filter.
Page 294 The pipeline registers are fed by the multiplier blocks. These registers can increase the DSP block performance, but are optional. The output registers register the DSP block output. These registers can increase the DSP block performance, but are optional. 7–8 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 295 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–4. Quartus II Software View of MegaWizard Implementation of a DSP Block in Four-Multipliers Adder Mode Each input register of the DSP block provides a shiftout output that connects to the shiftin input of the adjacent input register of the same DSP block.
Page 296 MegaCore program. The FIR Compiler is an easy-to-use, fully-integrated graphical user interface (GUI) based FIR filter design software. For more information on the FIR Compiler MegaCore, visit the Altera web site at www.altera.com and search for “FIR compiler” in the “Intellectual Property”...
Page 297 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–5. Serial Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks Notes (1), (2), Data input x(n) DSP block 1 h(0) Filter coefficients x(n-1) h(1) x(n-2) h(2) x(n-3)
Page 298 The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading. To increase the DSP block performance, include the input, pipeline, and output registers. See Figure 7–3 on page 7–8 for the details. 7–12 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 299: Time-Domain Multiplexed Fir Filters
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Basic FIR Filter Implementation Results Table 7–6 shows the results of the serial implementation of an 18-bit 8 tap FIR filter as shown in Figure 7–5 on page 7–11 Table 7–6.
Page 300 2x clock TDM Filter Implementation TDM FIR filters are implemented in Stratix and Stratix GX devices by configuring the DSP blocks in the multiplier-adder mode. Figure 7–9 shows the implementation of an 8-tap TDM FIR filter (n=2) with 18 bits of data and coefficient inputs.
Page 301 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices flops corresponding to h(0), h(2), h(4) and h(6) are enabled. This produces the temporary output, y , which is added to y to produce the overall output, y(n). The following shows what the overall output, y(n), equals:...
Page 302 The accumulator needs to be zeroed at the start of each new sample input. The user also needs a way to store additional sample inputs in memory. For example, consider a sample rate of r and TDM factor of 4. Then, the 7–16 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 303: Polyphase Fir Interpolation Filters
This section first describes interpolation filters and then how to implement them as polyphase filters in Stratix and Stratix GX devices. See the “Polyphase FIR Decimation Filters” on page 7–24...
Page 304 2 MHz and the interpolation factor (I) is 4. The Nyquist frequency of the upsampled signal must be greater than 8 MHz, and is chosen to be 9 MHz for this example. 7–18 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 305 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–11. Time & Frequency Domain Representations of Interpolation for I = 4 As an example, CD players use interpolation, where the nominal sample rate of audio input is 44.1 kilosamples per second. A typical implementation might have an interpolation (oversampling) factor of 4 generating 176.4 kilosamples per second of oversampled data stream.
Page 306 It is illuminating to compare the computational requirements of the direct implementation versus polyphase implementation of the low pass filter. In the direct implementation, the number of computations per cycle 7–20 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 307 Figure 7–12. The four polyphase filters share the same hardware, which is a 4-tap filter. One Stratix or Stratix GX DSP block can implement one 4-tap filter with 18-bit wide data and coefficients. A multiplexer can be used to load new coefficient values on ×...
Page 308 2, 6,... h(1), h(5), h(9), h(13) 0, 1, 2, 3 3, 7,... h(2), h(6), h(10), h(14) 0, 1, 2, 3 4, 8,... h(3), h(7), h(11), h(15) 0, 1, 2, 3 7–22 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 309 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–13. Implementation of the Polyphase Interpolation Filter (I=4) Notes (1), (2), Data input DSP block x(n) Filter coefficients h(0) RAM / ROM 0 h(1) RAM / ROM 1...
Page 310: Polyphase Fir Decimation Filters
The input rate is 60 MSPS, clocked in at 60MHz. Polyphase Interpolation Filter Design Example Download the Interpolation FIR Filter (interpolation_fir.zip) design example from the Design Examples section of the Altera web site at www.altera.com. Polyphase FIR Decimation Filters A decimation filter can be used to decrease the sample rate. A decimation filter is efficiently implemented with a polyphase FIR filter.
Page 311 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–14. Block Diagram Representation of Decimation Input Output sample rate f s sample rate f s /D Decimation filters reverse the effect of the interpolation filters. Before the decimation process, a low pass filter is applied to the signal to attenuate noise and aliases present beyond the Nyquist frequency.
Page 312 The polyphase implementation “splits” the original filter into D polyphase filters with impulse responses defined by the following equation. n ( ) 7–26 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 313 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices where: k = 0,1, …, D-1 n = 0,1, …, P-1 P = L/D = length of polyphase filters L is the length of the filter (selected to be a multiple of D)
Page 314 Polyphase Filter with coefficients h(2), h(6), h(10), h(14) Polyphase Filter with coefficients h(3), h(7), h(11), h(15) Modulo 4 down counter 4x clock initialized at 0 7–28 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 315 Polyphase Decimation Filter Implementation Figure 7–17 shows the decimation polyphase filter example of Figure 7–16 as it would fit into Stratix or Stratix GX DSP blocks. The coefficients of the polyphase filters need to be cycled using the schedule × shown in Table 7–13.
Page 316 DSP block (see Note (3)), and the accumulator block. To increase the DSP block performance, include the pipeline, and output registers. See Figure 7–3 on page 7–8 the details. 7–30 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 317: Complex Fir Filter
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Polyphase Decimation Filter Implementation Results Table 7–14 shows the results of the polyphase decimation filter implementation in a Stratix device shown in Figure 7–17. Table 7–14. Polyphase Decimation Filter Implementation Results...
Page 318 Complex FIR Filter Implementation Complex filters can be easily implemented in Stratix devices with the DSP blocks configured in the two-multipliers adder mode. One DSP block can implement a 2-tap complex FIR filter with 9-bit inputs, or a single tap complex FIR filter with 18-bit inputs.
Page 319 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices For more information on the different modes of the DSP blocks, see the DSP Blocks in Stratix & Stratix GX Devices chapter. Figure 7–19 shows an example of a 2-tap complex FIR filter design with 18-bit inputs.
Page 320: Infinite Impulse Response (Iir) Filters
The complications include phase distortion and finite word length effects, but these can be overcome by ensuring that the filter always operates within its intended range. Figure 7–20 shows a direct form II structure of an IIR filter. 7–34 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 321 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–20. Direct Form II Structure of an IIR Filter w(n) Σ Σ X(n) Y(n) Σ Σ Σ Σ Σ Σ The transfer function for an IIR filter is: i –...
Page 322: Basic Iir Filters
Basic IIR FIlter Implementation Multiplier blocks, adders and delay elements can implement a basic IIR filter. The Stratix architecture lends itself to IIR filters because of its embedded DSP blocks, which can easily be configured to perform these operations. The altmult_add megafunction can be used to implement the multiplier-adder mode in the DSP blocks.
Page 323 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–22. IIR Filter Biquad Note (1) Note to Figure 7–22: Unused ports are grayed out. Altera Corporation 7–37 September 2004 Stratix Device Handbook, Volume 2...
Page 324 DSP blocks. Figure 7–23. Two Cascaded Biquads First biquad Four-multipliers adder mode block 1 Two-multipliers adder mode x[n] Second biquad block 2 Four-multipliers adder mode y[n] block 3 7–38 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 325: Butterworth Iir Filters
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Basic IIR Filter Implementation Results Table 7–15 shows the results of implementing a 4 order IIR filter in a Stratix device. Table 7–15. 4 Order IIR Filter Implementation Results...
Page 326 It is possible to reduce the number of multipliers needed in each biquad to just two. 7–40 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 327 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Through the use of integer feedforward multiplies, which can be implemented by combining addition, shifting, and complimenting operations, a Butterworth filter’s transfer function biquad can be optimized for logic synthesis. The most efficient transformation is that of an all pole filter.
Page 328 7–24: Unused ports are grayed out. The z coefficient is a multiple of the other coefficients (z-2 and 1) in the feedforward path. This is implemented using a shift operation. 7–42 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 329 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices The DSP block in Figure 7–24 is configured in multiply and add mode. The three external adders are implemented in logic elements and therefore are not part of the DSP block. Therefore, for an 18-bit input, each biquad requires half a DSP block and three logic element adders.
Page 330 2 (n-1) y(n) w 2 (n-2) Note to Figure 7–25: The gain factor is compensated for at the end of the filtering stage and is not shown in this figure. 7–44 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 331: Matrix Manipulation
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Butterworth Filter Implementation Results Table 7–16 shows the results of implementing a 4 order Butterworth filter as shown in Figure 7–25. Table 7–16. 4 Order Butterworth Filter Implementation Results...
Page 332: Two-Dimensional Filtering & Video Imaging
Depending on the type of operation, the choice of the convolutional kernel or mask, f(k,l) is × different. Figure 7–26 shows an example of convolving a 3 3 mask with a larger image. 7–46 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 333 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices × Figure 7–26. Convolution Using a 3 3 Kernel The output pixel value, y(m,n) depends on the surrounding pixel values in the input image, as well as the filter weights:...
Page 334 M4K memory blocks. For larger images (640 480), this can be extended to M-RAM blocks or other buffering schemes. The control logic block provides the RAM control signals to interleave the data across all three 7–48 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 335 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices RAM blocks. The 9-bit signed filter coefficients feed directly into the filter block. As the data is shifted out from the RAM blocks, the multiplexer block checks for edge pixels and uses the free boundary condition.
Page 336 + 1, n ) DSP Block in Simple Multiplier Mode (8-bit) x(m + 1, n + 1) Note: Unused multipliers and adders grayed out. These multipliers can be used by other functions. 7–50 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 337 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices In cases where a symmetric 2-D filter is used, pixels sharing the same filter coefficients from three separate line-stores A, B, and C can be added together prior to the multiplication operation. This reduces the number of multipliers used.
Page 338: Discrete Cosine Transform (Dct)
Convolution Design Example × Download the 3 3 2-D Convolutional Filter (two_d_fir.zip) design example from the Design Examples section of the Altera web site at www.altera.com. Discrete Cosine The discrete cosine transform (DCT) is widely used in video and audio compression, for example in JPEG, MPEG video, and MPEG audio.
Page 339: 2-D Dct Algorithm
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices For 1-D with input data x(n) of size N, the DCT coefficients Y(k) are: – α k ( ) )πk ⎛ ⎞ ≤ ≤ ∑ ---------- - -------------------------- -...
Page 340 Sum a and b Multiplied by -1 Multiply-addition block C m1 Stage 3 output (S3) C m2 Matrix coefficent (C mn ) + ... + c π C mn where = cos 7–54 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 341 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices The following defines in matrix format, the 8-point 1-D DCT of Figure 7–33: × × × × where: × [x] is the 1 8 input matrix 1 0 0 0 0 0 0 1...
Page 342 1-D 8-point DCT algorithm, the hardware implementation shows this block as being shared. The DCT algorithm requires a serial-to-parallel conversion block at the input because it works on blocks of eight data 7–56 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 343 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices points in parallel. There is also a parallel-to-serial conversion block at the output because the column processing stage generates the output image column-by-column. In order to have the output in the same order as the input (i.e., row-by-row), this conversion is necessary.
Page 344 Performance 165 MHz Latency 80 clock cycles DCT Design Example Download the 2-D convolutional filter (d_dct.zip) design example from the Design Examples section of the Altera web site at www.altera.com. 7–58 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 345: Arithmetic Functions
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Arithmetic Arithmetic functions, such as trigonometric functions, including sine, cosine, magnitude and phase calculation, are important DSP elements. Functions This section discusses the implementation of a simple vector magnitude function in a Stratix device.
Page 346: Arithmetic Function Implementation
2. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In Stratix devices, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
Page 347 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–38. Implementing the Vector Magnitude Function DSP Block - Two Multipliers Adder Mode (9-bit) LE implemented square root function Note: Unused multipliers and adders grayed out. Altera Corporation 7–61...
Page 348: Arithmetic Function Implementation Results
Design Examples section of the Altera web site at www.altera.com. Conclusion The DSP blocks in Stratix and Stratix GX devices are optimized to support DSP functions requiring high data throughput, such as FIR filters, IIR filters and the DCT. The DSP blocks are flexible and configurable in different operation modes based on the application’s needs.
Page 349: References
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices References See the following for more information: ■ Optimal DCT for Hardware Implementation M. Langhammer. Proceedings of International Conference on Signal Processing Applications & Technology (ICSPAT) '95, October 1995 ■...
Page 350 References 7–64 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 351: Section V. Ip & Design Considerations
® by Altera for Stratix devices. (Also see the Intellectual Property section of the Altera web site for a complete offering of IP cores for Stratix devices.) The last chapter details design considerations for migrating ™ from the APEX architecture.
Page 352 ● Asynchronous occurrences renamed flow-through. November 2003, v1.2 ● Removed support for series and parallel on-chip termination. October 2003, v1.1 ● Updated Table 10–6. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. Section V–2 Altera Corporation...
Page 353: Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix Gx Devices
10-gigabit attachment unit interface (XAUI) using the embedded 3.125-Gbps transceivers. You can find more information on XAUI support in Section II, Stratix GX Transceiver User Guide, of the Stratix GX Device Handbook, Volume 1. This chapter discusses the following topics: ■...
Page 354 Notes to Figure 8–1: LLC: logical link controller MAC: media access controller PCS: physical coding sublayer PHY: physical layer PMA: physical medium attachment PMD: physical medium dependent MDI: medium dependent interface 8–2 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 355 Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices The Ethernet PHY (layer 1 of the OSI model) connects the media (optical or copper) to the MAC (layer 2). The Ethernet architecture further divides the PHY (layer 1) into a PMD sublayer, a PMA sublayer, and a PCS. For example, optical transceivers are PMD sublayers.
Page 356 Interface directly covered in this application note Interface indirectly covered in this application note RS (1) Can be implemented in Altera PLDs XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL) 8b/10b XGXS (2) XAUI (4 Bits at 3.125 Gbps PCML)
Page 357: Interfaces
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Interfaces The following sections discuss XSBI, PCS, XGMII, and XAUI. XSBI One of the blocks of 10-Gigabit Ethernet is the XSBI interface. XSBI is the interface between the PCS and the PMA sublayers of the PHY layer of the OSI model.
Page 358 Table 8–1. XSBI Clock & Data Rates for WAN & LAN PHY Parameter WAN PHY LAN PHY Unit 622.08 644.53125 Mbps TX_D[15..0] 622.08 644.53125 PMA_TXCLK 622.08 644.53125 PMA_TXCLK_SRC 622.08 644.53125 Mbps RX_D[15..0] 622.08 644.53125 PMA_RXCLK 8–6 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 359 DPA is disabled. However, it is simple to implement the same system with DPA enabled to take advantage of its features. For more information on DPA, see the Stratix GX Transceivers chapter in the Stratix GX Device Handbook, Volume 1.
Page 360 Figure 8–6 shows the transmitter output of the XSBI core. Data transmitted from the PCS to the PMA starts at the core of the Stratix or Stratix GX device and travels to the Stratix or Stratix GX transmitter SERDES block. The transmitter SERDES block converts the parallel data to serial data for 16 individual channels (TX_D[15..0]).
Page 361 Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Stratix and Stratix GX devices contain up to eight fast PLLs. These PLLs provide high-speed outputs for high-speed differential I/O support as well as general- purpose clocking with multiplication and phase shifting.
Page 362 Interfaces With this XSBI transmitter and receiver block implementation, each XSBI core requires two fast PLLs. The potential number of XSBI cores per device corresponds to the number of fast PLLs each Stratix or Stratix GX device contains. Tables 8–2 8–3...
Page 363 The high speed LVDS channels can go up to 840 Mbps. The low speed LVDS channels can go up to 462 Mbps. The High-Speed Differential I/O Support chapter in the Stratix Device Handbook, Volume 1, and the device pin-outs on the web (www.altera.com) specify which channels are high and low speed.
Page 364 PMA_TX_CLK PCS transmitter channel-to-channel skew Figure 8–9 shows the AC timing diagram for the Stratix and Stratix GX PCS receiver interface. You can determine the PCS sampling window by adding T to T . Receiver skew margin (RSKM) refers to the amount...
Page 365: Xgmii
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Table 8–5. PCS Receiver Timing Specifications (Part 2 of 2) Value Parameter Unit duty cycle PMA_RX_CLK Data set-up time (T setup Data hold time (T hold PCS sampling window RSKM (WAN)
Page 366 Implementation XGMII uses the 1.5-V HSTL I/O standard. Stratix and Stratix GX devices support the 1.5-V HSTL Class I and Class II I/O standard (EIA/JESD8-6). The standard requires a differential input with an external reference voltage (V ) of 0.75 V, as well as a termination voltage V...
Page 367 PCS to the MAC reconciliation sublayer starts at the core of the Stratix or Stratix GX device and travels to the shift register. The shift register takes in the parallel data (even bits sent to the top register and odd bits sent to the bottom register) and serializes the data.
Page 368 PLL. This data and clock go to the Stratix and Stratix GX core. This implementation shows only one channel, but can be duplicated to include all 32 bits of the TX_D signal and all 4 bits of the TX_C signal.
Page 369 PLL for both the XGMII output and input blocks. For more information about fast PLLs, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 370 EP1SGX40 D, G Reduced System Noise The output buffer of each Stratix and Stratix GX device I/O pin has a programmable drive strength control for certain I/O standards. The 1.5- V HSTL Class I standard supports the minimum setting, which is the...
Page 371: Xaui
The actual set-up and hold times will be made available after device characterization is complete. Stratix and Stratix GX devices support DDR data with clock rates of up to 200 MHz, well above the XGMII clock rate of 156.25 MHz. For the HSTL Class I I/O standard, Stratix and Stratix GX device I/O drivers provide a 1.0-V/ns slew rate at the input buffer of the receiving device.
Page 372 To support 10-Gigabit Ethernet, each lane must run at a speed of at least 2.5 Gbps. Using 8b/10b encoding increases the rate for each lane to 3.125 Gbps, which will be supported in Stratix GX Gbps devices. This circuitry is supported by the embedded 3.125 Gbps transceivers within the Stratix GX architecture.
Page 373 Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices information on XAUI support in Section II, Stratix GX Transceiver User Guide of the Stratix GX Device Handbook, Volume 2. Figure 8–16 shows how XAUI is implemented. Figure 8–16. Stratix GX XAUI Implementation...
Page 374: I/O Characteristics For Xsbi, Xgmii & Xaui
Table 8–10: Larger V is possible for better signal intensity. I/O characteristics for the 1.5-V HSTL standard for Stratix and Stratix GX devices are shown in Figure 8–17 and comply with XGMII electrical specifications available in 10-Gigabit Ethernet draft IEEE P802.3ae.
Page 375 Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Figure 8–17. Electrical Characteristics for Stratix & Stratix GX Devices (1.5-V HSTL Class I) 80% V (min) = 1 V/ns (min) = 1 V/ns SWING SWING = 1.0 V Input 20% V SWING −...
Page 376: 10-Gigabit Ethernet Mac Core
Drive strength is programmable according to values shown in the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 377: Conclusion
Conclusion 10-Gigabit Ethernet takes advantage of the existing Gigabit Ethernet standard. With their rich I/O features, Stratix and Stratix GX devices support the components of 10-Gigabit Ethernet as well as XSBI and XGMII. Stratix GX devices also support XAUI. These interfaces are easily implemented using the core architecture, differential I/O capabilities, and superior PLLs of Stratix and Stratix GX devices.
Page 378 I/O Characteristics for XSBI, XGMII & XAUI 8–26 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 379: Chapter 9. Implementing Sfi-4 In Stratix & Stratix Gx Devices
9. Implementing SFI-4 in Stratix & Stratix GX Devices S52011-2.0 Introduction The growth of the Internet has created huge bandwidth demands as voice, video, and data push the limits of the existing wide area network (WAN) backbones. To facilitate this bandwidth growth, speeds of OC-192...
Page 380 The mapper following the framer maps asynchronous transfer mode (ATM) cells, IP packets, or T/E carrier signals into the SONET frame. The PHY-link layer interface provides a bus interface to packet/cell processors or other link-layer devices. 9–2 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 381: System Topology
Figure 9–2. An aggregate of 9953.28 Mbps is transferred in each direction. With their differential I/O capabilities, Stratix and Stratix GX devices are ideally suited to support the framer side of the SFI-4 interface. Support for SFI-4 extends the reach of high-density programmable logic from the backplane to the PHY devices.
Page 382 Table 9–1. SFI-4 Interface Data Rates & Clock Frequencies Signal Performance 622.08 Mbps TXDATA[15..0] 622.08 MHz or 311.04 MHz TXCLK 622.08 MHz TXCLK_SRC 622.08 Mbps RXDATA[15..0] 622.08 MHz RXCLK 622.08 MHz REFCLK 9–4 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 383: Interface Implementation In Stratix & Stratix Gx Devices
DPA is disabled. However, it is simple to implement the same system with DPA enabled to take advantage of its features. For more information on DPA, see the Stratix GX Transceivers chapter in the Stratix GX Device Handbook, Volume 1.
Page 384 9–4) of the SFI-4 framer interface implemented in Stratix and Stratix GX devices. The data starts in the logic array and goes into the Stratix and Stratix GX SERDES block. The transmitter SERDES of the framer converts the parallel data to serial data for the 16 TXDATA channels (TXDATA[15..0]).
Page 385 Stratix and Stratix GX devices. RXDATA[15..0] is received from the OC-192 SERDES on the differential I/O pins of the Stratix or Stratix GX device. The receiver SERDES converts the high-speed serial data to parallel. You can generate the clocks required in the SERDES for parallel and serial data conversion from the received RXCLK.
Page 386 The figure shows Stratix GX DPA disabled. For more information on the byte-alignment feature in Stratix and Stratix GX devices, see the High-Speed Differential I/O Interfaces in Stratix Devices chapter in the Stratix Device Handbook or the Stratix GX Device Handbook. 9–8...
Page 387 Table 9–2: The LVDS channels can go up to 840 Mbps (or 1 Gbps using DPA in Stratix GX devices). This number includes both high speed and low speed channels. The high speed LVDS channels can go up to 840 Mbps. The low speed LVDS channels can go up to 462 Mbps.
Page 388: Ac Timing Specifications
For details on the timing specifications of LVDS I/O standards in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the High-Speed Differential I/O Interfaces in Stratix Devices chapter or the Stratix GX Device Family Data...
Page 389 Implementing SFI-4 in Stratix & Stratix GX Devices Figure 9–8 shows the timing diagram for the SFI-4 framer transmitter in × 2 (311 MHz clock) mode Figure 9–8. Framer Transmitter × 2 (311 MHz Clock) Mode Timing Diagram T period/2...
Page 390: Electrical Specifications
IEEE Std. 1596.3-1996 7 specification. For more information on the voltage specification of LVDS I/O standards in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the High-Speed...
Page 391: Software Implementation
10-Gbps (OC-192) data transfer rates. Stratix and Stratix GX I/O supports the required data rates of up to 622.08 Mbps. Stratix and Stratix GX fast PLLs are designed to support the high clock frequencies and one-to-one relationship needed for interfaces such as XSBI and SFI-4. Stratix and Stratix GX devices can support multiple SFI-4 functions on one device.
Page 392 Introduction 9–14 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 393: Chapter 10. Transitioning Apex Designs To Stratix & Stratix Gx Devices
This chapter highlights the new features in the Stratix and Stratix GX devices and provides assistance when transitioning designs from APEX II or APEX 20K devices to the Stratix or Stratix GX architecture.
Page 394: Logic Elements
General Architecture Logic Elements Stratix and Stratix GX device LEs include several new, advanced features that improve design performance and reduce logic resource consumption (see Table 10–1). The Quartus II software automatically uses these new LE features to improve device utilization.
Page 395: Multitrack Interconnect
Transitioning APEX Designs to Stratix & Stratix GX Devices cascade primitives in APEX II and APEX 20K designs to a wire primitive when compiled for Stratix and Stratix GX devices. These architectural changes are transparent to the user and do not require design changes.
Page 396: Directdrive Technology
Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
Page 397: Architectural Element Names
(for example, LC1_A2, LAB_B1) used in previous Altera device families. Stratix and Stratix GX devices uses a new naming system based on the X-Y coordinate system, (X, Y). A number (N) designates the location within the block where the logic resides, such as LEs within an LAB.
Page 398 You can make assignments to I/O pads using IOC_X<number>_Y<number>_N<number>. Use the following guidelines with the new naming system: ■ The anchor point, or origin, in Stratix and Stratix GX devices is in the bottom-left corner, instead of the top-left corner as in APEX II and APEX 20K devices.
Page 399 Figure 10–2 shows part of a Stratix and Stratix GX device. Large block elements use their lower-left corner for the coordinate location. The Stratix GX architectural elements include transceiver blocks on the right side of the device. Altera Corporation 10–7...
Page 400: Trimatrix Memory
(ESBs) either 4 Kbits (APEX II devices) or 2 Kbits (APEX 20K devices) large. Stratix and Stratix GX TriMatrix memory blocks give you advanced control of each memory block, with features such as byte enables, parity bit storage, and shift-register mode, as well as mixed-port width support and true dual-port mode operation.
Page 401 Transitioning APEX Designs to Stratix & Stratix GX Devices Table 10–4 compares TriMatrix memory with ESBs. Table 10–4. Stratix & Stratix GX TriMatrix Memory Blocks vs. APEX II & APEX 20K ESBs Stratix & Stratix GX Features APEX II ESB...
Page 402: Same-Port Read-During-Write Mode
For more information about TriMatrix memory and converting flow- through memory modules to pipelined, see the TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices chapter in the Stratix GX Device Handbook and AN 210: Converting Memory from Asynchronous to Synchronous for Stratix &...
Page 403: Mixed-Port Read-During-Write Mode
Figure 10–6 assumes that outputs are not registered. Stratix and Stratix GX device RAM outputs the new data on the rising edge of the clock cycle immediately after the data was written. When you use Stratix and Stratix GX M512 and M4K blocks, you can choose whether to output the old data at the targeted address or output a don’t care value...
Page 404: Memory Megafunctions
Memory Megafunctions To convert RAM and ROM originally targeting the APEX II or APEX 20K architecture to Stratix or Stratix GX memory, specify Stratix or Stratix GX as the target family in the MegaWizard Plug-In Manager. The software 10–12...
Page 405: Fifo Conditions
Transitioning APEX Designs to Stratix & Stratix GX Devices updates the memory module for the Stratix or Stratix GX architecture and instantiates the new synchronous memory megafunction, altsyncram, which supports both RAM and ROM blocks in the Stratix and Stratix GX architectures. FIFO Conditions First-in first-out (FIFO) functionality is slightly different in Stratix and Stratix GX devices compared to APEX II and APEX 20K devices.
Page 406 A port is reading from an address that is being written to by another port (mixed-port read-during-write mode). If both ports are using the same clock, the read port in Stratix and Stratix GX devices do not see the new data until the next clock cycle, after the new data was written.
Page 407 Transitioning APEX Designs to Stratix & Stratix GX Devices ■ There are differences in power-up behavior between APEX II, APEX 20K, and Stratix and Stratix GX devices. You should manually account for these differences to maintain desired operation of the system.
Page 408: Dsp Block
DSP block resource consumption, the width of the multiplier, whether an operand is a constant, and other options chosen for the megafunction. Stratix and Stratix GX devices do not support the Use ESBs option. If you select this option, the Quartus II software tries to place the multiplier in unused DSP blocks.
Page 409 LE resources for the additional pipeline stages. Therefore, if multiplier modules in APEX II or APEX 20K designs are converted to Stratix or Stratix GX designs and do not require the same number of pipeline stages, the surrounding circuitry must be modified to preserve the original functionality of the design.
Page 410: Plls & Clock Networks
LEs. Depending on the synthesis tools, inference of DSP blocks is handled differently. For more information about using DSP blocks in Stratix and Stratix GX devices, see the DSP Blocks in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. PLLs & Clock...
Page 411: Plls
Stratix and Stratix GX PLL enhancements to existing APEX II, APEX 20KE and APEX 20KC PLL features. Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 1 of 2) Stratix & Stratix GX APEX 20KE &...
Page 412 PLLs & Clock Networks Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 2 of 2) Stratix & Stratix GX APEX 20KE & Feature APEX II PLLs APEX 20KC PLLs Enhanced PLLs...
Page 413 If the PLL is used in external feedback mode, the PLL will need to relock. Fast PLLs Stratix and Stratix GX fast PLLs are similar to the APEX II True-LVDS PLLs in that the W setting, which governs the relationship between the...
Page 414 Table 10–8 shows the differences between Stratix and Stratix GX fast PLLs and APEX II and APEX 20K True-LVDS PLLs. Table 10–8. Stratix & Stratix GX Fast PLL vs. APEX II & APEX 20K True-LVDS PLL APEX 20KE Feature Stratix & Stratix GX...
Page 415 10–9). The altclklock megafunction is also available from the Quartus II software for backward compatibility, but instantiates the new altpll megafunction when targeting Stratix or Stratix GX devices. The Quartus II Compiler automatically selects whether the altpll module uses either an enhanced PLL or a fast PLL based on the design’s PLL needs and the feature requirements of each PLL.
Page 416 Quartus II Compiler does not know which PLL clock output is fed to an external output pin or fed back to the Stratix or Stratix GX device fbin pin. For example, if an APEX II, APEX 20KE, or APEX 20KC design with...
Page 417: I/O Structure
DQ pins depends on the DQ bus mode. When using the external RAM interfacing circuitry, the DQS pin drives a dedicated clock network that feeds the DQ pins residing in that bank. The Stratix and Stratix GX IOE has programmable delay chains that can phase shift the DQS signal by 90° or 72°...
Page 418: I/O Standard Support
Stratix and Stratix GX devices only support certain I/O standards in designated I/O banks. In addition, vref pins are dedicated pins in Stratix and Stratix GX devices and now support up to 40 input pins. For more information about I/O standard support in Stratix and Stratix GX devices, see the Selectable I/O Standards in Stratix &...
Page 419 Note to Table 10–9: For information on channel speeds, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the High-Speed Differential I/O Interfaces chapter in the Stratix Device Handbook, Volume 2. Altera Corporation 10–27...
Page 420 Note to Table 10–10: For information on channel speeds, see the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 and the High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2.
Page 421: Altlvds Megafunction
Indicates the fast PLL can be shared between receiver and transmitter common_rx_tx_pll applications. Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 1 of 2) Note (1) Parameter Function Specifies the data rate in Mbps. This parameter replaces the output_data_rate multiplication factor W.
Page 422: Configuration
Configuration Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2) Note (1) Parameter Function Specifies the clock source for the input synchronization registers, registered_input which can be either . Used only tx_inclock tx_coreclock when the Registered Inputs option is selected.
Page 423: Remote Update Configuration
If an error occurs either during device configuration or in user mode, this new circuitry reconfigures the Stratix or Stratix GX device to a known state. Additionally, the Stratix and Stratix GX devices have a user watchdog timer to ensure the application configuration data executes successfully during user mode.
Page 424: Conclusion
APEX II and APEX 20K device families to deliver a complete system-on-a-programmable-chip (SOPC) solution. By following these guidelines, you can easily transition current APEX II and APEX 20K designs to take advantage of the new features available in Stratix and Stratix GX devices. 10–32...
Page 425: Section Vi. System Configuration & Upgrades
■ Chapter 11, Configuring Stratix & Stratix GX Devices ■ Chapter 12, Remote System Configuration with Stratix & Stratix GX Devices For information on Altera enhanced configuration devices, see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet chapter in the Configuration Handbook, Volume 2.
Page 426: Revision History
System Configuration & Upgrades Stratix Device Handbook, Volume 2 Revision History The table below shows the revision history for Chapters 11 through 12. Chapter Date/Version Changes Made July 2005, v3.2 ● Updated “PORSEL Pins” “nIO_PULLUP Pins” sections. ● Updated “FPP Configuration Using an Enhanced Configuration Device”...
Page 427: Chapter 11. Configuring Stratix & Stratix Gx Devices
Ability to use ® SignalTap II Embedded Logic Analyzer. This chapter discusses how to configure one or more Stratix or Stratix GX devices. It should be used together with the following documents: ■ MasterBlaster Serial/USB Communications Cable Data Sheet ■...
Page 428: Device Configuration Overview
CONF_DONE goes low after nCONFIG is driven low. User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistor on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform the function assigned in the user’s design.
Page 429: Msel[2..0] Pins
Pins CCSEL You can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-, or 1.5-V LVTTL I/O standard on configuration and JTAG input pins. VCCSEL is a dedicated input on Stratix and Stratix GX devices that selects between 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers for...
Page 430 I/O bank containing the pin. After CCIO configuration, the dual-purpose pins inherit the I/O standards specified in the design. 11–4 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 431: Porsel Pins
1-kΩ resistor. When using enhanced configuration devices to configure Stratix devices, make sure that the PORSEL setting of the Stratix device is the same or faster than the PORSEL setting of the enhanced configuration device. If...
Page 432: Tdo & Nceo Pins
Configuration Tables 11–5 11–6 summarize the approximate configuration file size required for each Stratix and Stratix GX device. To calculate the amount File Size of storage space required for multi-device configurations, add the file size of each device together. Table 11–5. Stratix Configuration File Sizes Device Raw Binary File (.rbf) Size (Bits)
Page 433: Altera Configuration Devices
Altera configuration device, or a download cable. In the PS scheme, an external host (MAX device, embedded processor, configuration device, or host PC) controls configuration. Configuration data is clocked into the target Stratix devices via the DATA0 pin at each rising edge of DCLK. Altera Corporation 11–7...
Page 434 Configuration Schemes PS Configuration with Configuration Devices The configuration device scheme uses an Altera configuration device to supply data to the Stratix or Stratix GX device in a serial bitstream (see Figure 11–3). In the configuration device scheme, nCONFIG is usually tied to V (when using EPC16, EPC8, EPC4, or EPC2 devices, nCONFIG may be connected to nINIT_CONF).
Page 435 When CONF_DONE is driven low after device configuration, the configuration device recognizes that the target device has not configured successfully. Figure 11–2 shows how to configure one Stratix or Stratix GX device with one configuration device. Altera Corporation 11–9...
Page 436 EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the nINIT_CONF pin. Figure 11–3 shows how to configure multiple Stratix and Stratix GX devices with multiple EPC2 or EPC1 configuration devices. 11–10 Altera Corporation...
Page 437 OE pin low for a few microseconds. This low pulse drives the OE pin low on the second configuration device and drives nSTATUS low on all Stratix and Stratix GX devices, causing them to enter an error state. If the Auto-Restart Configuration on Frame Error option is turned on in the software, the Stratix or Stratix GX device releases its nSTATUS pins after a reset time-out period.
Page 438 Configuration Schemes Restart Configuration on Frame Error option is not turned on, the Stratix or Stratix GX devices drive nSTATUS low until they are reset with a low pulse on nCONFIG. You can also cascade several EPC2/EPC1 configuration devices to configure multiple Stratix and Stratix GX devices.
Page 439 Configuring Stratix & Stratix GX Devices Figure 11–4. Configuring Multiple Stratix & Stratix GX Devices with A Single Configuration Device Note (1) V CC V CC V CC 10 kΩ 10 kΩ Configuration Stratix or Stratix GX Device 1 Device (4)
Page 440 PS Configuration with a Download Cable In PS configuration with a download cable, an intelligent host transfers data from a storage device to the Stratix or Stratix GX device through the MasterBlaster, USB-Blaster, ByteBlaster II or ByteBlasterMV cable. To initiate configuration in this scheme, the download cable generates a low-to-high transition on the nCONFIG pin.
Page 441 . This pin is a no-connect pin for the ByteBlasterMV header. CCIO You can use programming hardware to configure multiple Stratix and Stratix GX devices by connecting each device’s nCEO pin to the subsequent device’s nCE pin. All other configuration pins are connected to each device in the chain.
Page 442 Figure 11–7 shows a combination of a configuration device and a download cable to configure a Stratix or Stratix GX device. 11–16 Altera Corporation Stratix Device Handbook, Volume 2...
Page 443 . This is a no-connect pin for the ByteBlasterMV header. CCIO You should not attempt configuration with a download cable while a configuration device is connected to a Stratix or Stratix GX device. Instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device.
Page 444 PS Configuration with a Microprocessor In PS configuration with a microprocessor, a microprocessor transfers data from a storage device to the target Stratix or Stratix GX device. To initiate configuration in this scheme, the microprocessor must generate a low-to-high transition on the nCONFIG pin and the target device must release nSTATUS.
Page 445 N.C. DATA0 nCONFIG DCLK PS Configuration Timing Figure 11–9 shows the PS configuration timing waveform for Stratix and Stratix GX devices. Table 11–8 shows the PS timing parameters for Stratix and Stratix GX devices. Altera Corporation 11–19 July 2005...
Page 446 Configuration Schemes Table 11–8. PS Timing Parameters for Stratix & Stratix GX Devices Symbol Parameter Units nCONFIG low to CONF_DONE CF2CD low to nCONFIG nSTATUS CF2ST0 high to high µs nCONFIG nSTATUS CF2ST1 µs nCONFIG low pulse width µs low pulse width...
Page 447: Fpp Configuration
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay. Upon power-up, before and during configuration, CONF_DONE is low.
Page 448 Configuration Schemes FPP Configuration Using an Enhanced Configuration Device When using FPP with an enhanced configuration device, it supplies data in a byte-wide fashion to the Stratix or Stratix GX device every DCLK cycle. See Figure 11–10. Figure 11–10. FPP Configuration Using Enhanced Configuration Devices 10 kΩ...
Page 449 Stratix GX device has not configured successfully. The enhanced configuration device pulses its OE pin low for a few microseconds, driving the nSTATUS pin on the Stratix or Stratix GX device low. If the Auto-restart configuration after error option is on, the Stratix or Stratix GX device resets and then pulses its nSTATUS low.
Page 450 OE low for a few microseconds to reset the chain. The low OE pulse drives nSTATUS low on all Stratix and Stratix GX devices, causing them to enter an error state. This state is similar to a Stratix or Stratix GX device detecting an error.
Page 451 For timing information, see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet. The configuration device drives DATA high after configuration. Stratix and Stratix GX devices enter user mode 136 clock cycles after CONF_DONE goes high. FPP Configuration Using a Microprocessor...
Page 452 CLKUSR continues toggling during the time nSTATUS is low (maximum of 40 µs). If the Stratix or Stratix GX device detects an error during configuration, it drives nSTATUS low to alert the microprocessor. The pin on the microprocessor connected to nSTATUS must be an input. The microprocessor can then pulse nCONFIG low to restart the configuration error.
Page 453 ) specification. For multi-device parallel configuration with a microprocessor, the nCEO pin of the first Stratix or Stratix GX device is cascaded to the second device’s nCE pin. The second device in the chain begins configuration within one clock cycle; therefore, the transfer of data destinations is transparent to the microprocessor.
Page 454 Stratix high-level input voltage (V specification. The nCEO pins are left unconnected when configuring the same data into multiple Stratix or Stratix GX devices. For more information on configuring multiple Altera devices in the same configuration chain, see the Configuring Mixed Altera FPGA Chains chapter in the Configuration Handbook, Volume 2.
Page 455 CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay. Upon power-up, before and during configuration, CONF_DONE is low.
Page 456: Ppa Configuration
Configuration Schemes Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 2 of 2) Symbol Parameter Units DCLK frequency µs high to user mode CONF_DONE CD2UM low to nCONFIG CONF_DONE CF2CD nCONFIG low to nSTATUS CF2ST0 µs...
Page 457 Figure 11–16: The pull-up resistor should be connected to the same supply voltage as the Stratix or Stratix GX device. The device’s nCS or CS pins can be toggled during PPA configuration if the design meets the specifications for t...
Page 458 Quartus II software, select Device & Pin Option (Compiler Setting menu). If the Stratix or Stratix GX device detects an error during configuration, it drives nSTATUS low to alert the microprocessor. The microprocessor can then pulse nCONFIG low to restart the configuration process.
Page 459 If not used, you can connect the CS pin to V directly. If not used, the nCS pin can be connected to GND directly. Connect the pull-up resistor to the same supply voltage as the Stratix or Stratix GX device. Altera Corporation 11–33...
Page 460 Upon power-up, nSTATUS is held low for the time of the POR delay. Upon power-up, before and during configuration, CONF_DONE is low. After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or Stratix GX device.
Page 461 Configuring Stratix & Stratix GX Devices Figure 11–19 shows the Stratix and Stratix GX timing waveforms when using strobed nRS and nWS signals. Figure 11–19. PPA Timing Waveforms Using Strobed nRS & nWS Signals CF2ST1 nCONFIG nSTATUS CF2ST0 STATUS CF2SCD...
Page 462: Jtag Programming & Configuration
Configuration Schemes Table 11–10 defines the Stratix and Stratix GX timing parameters for PPA configuration Table 11–10. PPA Timing Parameters for Stratix & Stratix GX Devices Symbol Parameter Units high to first rising edge on µs nCONFIG CF2WS Data setup time before rising edge on...
Page 463 ® To use the SignalTap II embedded logic analyzer, you need to connect the JTAG pins of your Stratix device to a download cable header on your PCB. For more information on SignalTap II, see the Design Debugging Using SignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook, Volume 2.
Page 464 This scheme enables the programming software to program or verify the target device. Configuration data driven into the device appears on the TDO pin one clock cycle later. 11–38 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 465: Jtag Programming & Configuration Of Multiple Devices
Configuring Stratix & Stratix GX Devices Stratix and Stratix GX devices have dedicated JTAG pins. You can perform JTAG testing on Stratix and Stratix GX devices before and after, but not during configuration. The chip-wide reset and output enable pins on Stratix and Stratix GX devices do not affect JTAG boundary-scan or programming operations.
Page 466 JTAG configured in the same order as the multi-device configuration chain, the nCEO of the previous device drives nCE of the next device low when it has successfully been JTAG configured. 11–40 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 467: Configuration With Jrunner Software Driver
JTAG, allow any non-JTAG configuration to complete first. Figure 11–22 shows the JTAG configuration of a Stratix or Stratix GX device with a microprocessor. Figure 11–22. JTAG Configuration of Stratix & Stratix GX Devices with a Microprocessor Stratix or Memory Stratix GX Device...
Page 468: Jam Stapl Programming & Test Language
PLD. In this method, the JTAG chain becomes an address on the existing bus. The processor then reads from or writes to the address representing the JTAG chain. 11–42 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 469 Both JTAG connection methods should include space for the MasterBlaster or ByteBlasterMV header connection. The header is useful during prototyping because it allows you to verify or modify the Stratix or Stratix GX device’s contents. During production, you can remove the header to save cost.
Page 470 TCK, and uses the TMS pin to control JTAG operation in a device. Figure 11–24 shows the flow of an IEEE Std. 1149.1 TAP controller state machine. 11–44 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 471 Configuring Stratix & Stratix GX Devices Figure 11–24. JTAG TAP Controller State Machine TEST_LOGIC/ TMS = 1 RESET TMS = 0 TMS = 1 SELECT_DR_SCAN SELECT_IR_SCAN TMS = 1 TMS = 1 RUN_TEST/ TMS = 0 IDLE TMS = 0...
Page 472 The flow diagram shows branches for the DRSCAN, IRSCAN, and WAIT instructions. Although the Jam Player supports other instructions, they are omitted from the flow diagram for simplicity. 11–46 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 473 Configuring Stratix & Stratix GX Devices Figure 11–25. Jam Player Flow Diagram (Part 1 of 2) Start Set TMS to 1 and Pulse TCK Five Times Test-Logic-Reset Set TMS to 0 and Pulse TCK Run-Test/Idle Switch WAIT DRSCAN Case[] Read Instruction...
Page 474 The Jam language does not support linking multiple Jam programs together or including the contents of another file into a Jam program. 11–48 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 475 Configuring Stratix & Stratix GX Devices Jam Instructions Each Jam statement begins with one of the instruction names listed in Table 11–13. The instruction names, including the names of the optional instructions, are reserved keywords that you cannot use as variable or label identifiers in a Jam program.
Page 476 IRSCAN 10, I_IDCODE[0..9]; ‘LOAD IDCODE INSTRUCTION STATE IDLE; WAIT 5 USEC, 3 CYCLES; DRSCAN 32, ONES_DATA[0..31], CAPTURE read_data[0..31]; ‘CAPTURE IDCODE PRINT “IDCODE:”; FOR i=0 to 31; PRINT read_data[i]; NEXT i; EXIT 0; 11–50 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 477: Configuring Using The Microblaster Driver
Some of Pins these pins may not be required for your configuration schemes. Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 1 of 8) Configuration Pin Name...
Page 478 Device Configuration Pins Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 2 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Input Dedicated input that chooses whether the nIO_PULLUP internal pull-ups on the user I/Os and dual- purpose I/Os ( DATA[7..0]...
Page 479 Configuring Stratix & Stratix GX Devices Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 3 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Bidirectional The device drives low immediately nSTATUS nSTATUS open-drain after power-up and releases it after the POR time.
Page 480 Device Configuration Pins Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 4 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Bidirectional Status output. The target FPGA drives the CONF_DONE open-drain CONF_DONE pin low before and during configuration.
Page 481 Configuring Stratix & Stratix GX Devices Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 5 of 8) Configuration Pin Name User Mode Pin Type Description Scheme All Multi- Output Output that drives low when device...
Page 482 Device Configuration Pins Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 6 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Parallel Inputs Data inputs. Byte-wide configuration data is DATA[7..1] configuration presented to the target device on schemes .
Page 483 Configuring Stratix & Stratix GX Devices Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 7 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Input Read strobe input. A low input directs the...
Page 484 Device Configuration Pins Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 8 of 8) Configuration Pin Name User Mode Pin Type Description Scheme Input Chip-select inputs. A low on and a high on nCS/CS select the target device for configuration.
Page 485 Configuring Stratix & Stratix GX Devices Table 11–16 describes the optional configuration pins. If these optional configuration pins are not enabled in the Quartus II software, they are available as general-purpose user I/O pins. Therefore during configuration, these pins function as user I/O pins and are tri-stated with weak pull-ups.
Page 486 Std. 1149.1. If the JTAG interface is not required on the board, the JTAG circuitry can be disabled by connecting this pin to GND. This pin uses Schmitt trigger input buffers. 11–60 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 487: Chapter 12. Remote System Configuration With Stratix & Stratix Gx Devices
Remote Remote system configuration has three major parts: Configuration ■ The Stratix or Stratix GX device receives updated or new data from a remote source over a network (or through any other source that can Operation ® transfer data). You can implement a Nios™ (16-bit ISA) or Nios...
Page 488 Remote Configuration Operation Figure 12–1. Remote System Configuration with Stratix & Stratix GX Devices Network Stratix or Data Development Stratix GX Memory Location Data Device Control Module Data Stratix Device Configuration Figure 12–2. Different Options for Remote System Configuration Enhanced External MAX Device &...
Page 489: Remote System Configuration Modes
Table 12–1: For detailed information on standard PS, FPP, and PPA models, see the Configuring Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2. In Stratix and Stratix GX devices, the RUnLU (remote update/local update) pin, selects between local or remote configuration mode.
Page 490 Remote Configuration Operation page address of the application configuration that should be loaded into the Stratix or Stratix GX device. If an error occurs during user mode of an application configuration, the device reloads the default factory configuration page. Figure 12–3 shows a diagram of remote configuration mode.
Page 491: Remote System Configuration Components
A description of each component follows. Page Mode Feature The page mode feature enables Stratix and Stratix GX devices to select a location to read back data for configuration. The enhanced configuration device can receive and store up to eight different configuration files (one factory and seven application files).
Page 492 Remote Configuration Operation Figure 12–5. Page Mode Feature in Stratix or Stratix GX Devices & Enhanced Configuration Devices Enhanced Configuration Device POF 8 tix7 Stratix or POF 1 Stratix GX Stratix 1 Device Page0 Page Select Upon power-up in remote configuration mode, the factory configuration (see description below) selects the user-specified page address through the Stratix or Stratix GX PGM[2..0] output pins.
Page 493 12 bits to set the value for the watchdog timer. You specify the counter value according to your design needs. The timer begins counting once the Stratix or Stratix GX device goes into user mode. If the application configuration does not reset the user watchdog timer after the specified time, the timer times-out.
Page 494 Figure 12–6 shows the control, update, shift, and status registers and the data path used to control remote system configuration. 12–8 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 495 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–6. Remote Configuration Registers & Related Data Path Status Register Control Register Bit4...Bit10 Bit16...Bit0 Logic to Reconfig Logic Update Register Bit0...Bit16 User Watchdog Timer Shift Register Control Logic RU_Dout RU_shftnhld...
Page 496 (POR). The difference between local configuration and remote configuration is how the control register is updated during a re-configuration and which core signals are enabled. 12–10 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 497 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–7. Remote System Configuration Control Register Table 12–4 shows the content of the control register upon POR. Table 12–4. Control Register Contents Parameter Definition POR Reset Value Comment Current configuration is factory or 1 bit ‘1’...
Page 498: Quartus Ii Software Support
Table 12–5: Core re-configuration enforces the system to load the application configuration data into the Stratix or Stratix GX device. This occurs after factory configuration specifies the appropriate application configuration data. Quartus II The Quartus II software supports implementation of both remote and local configuration modes in your Stratix or Stratix II device.
Page 499 (what-you-see-is-what-you-get) atom into your design. Without this atom or megafunction, you are not be able to access the dedicated remote configuration circuitry or registers within the Stratix or Stratix GX device. Figure 12–10 for a symbol of the altremote_update megafunction.
Page 500: Altremote_Update Megafunction
This signal is not affected by the busy signal and can reset the timer even when the remote update block is busy. If this port is left connected, the default value is 0. 12–14 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 501 Remote System Configuration with Stratix & Stratix GX Devices Table 12–6. Input Ports of the altremote_update Megafunction (Part 2 of 2) Port Name Required Source Description read_param Logic Array Once read_param is sampled as a logic high, the busy signal is asserted.
Page 502 Watchdog 1 bit '0 User watchdog timer enable. Writing of this Enable parameter is only allowed when in the factory configuration 12–16 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 503: Remote Update Wysiwyg Atom
Remote System Configuration with Stratix & Stratix GX Devices Table 12–8. Parameter Settings for the altremote_update Megafunction (Part 2 of 2) width of Selected param[2..0] POR Reset parameter Description Parameter bit setting Value value Page select 3 bit '001' - Local Page mode selection.
Page 504 Quartus II Software Support The Stratix and Stratix GX remote update atom ports are: Stratix_rublock <rublock_name> .clk(<clock source>), .shiftnld(<shiftnld source>), .captnupdt(<shiftnld source>), .regin(<regin input source from the core>), .rsttimer(<input signal to reset the watchdog timer>), .config(<input signal to initiate configuration>), .regout(<data output destination to core>),...
Page 505: Using Enhanced Configuration Devices
(PGM[2..0]), which provide access to all eight pages. Because the PGM[2..0] pins of an enhanced configuration device connect to the same pins of the Stratix or Stratix GX device, the Stratix or Stratix GX device selects one of the eight memory pages as a target location to read from.
Page 506 ECP16 enhanced configuration device, and then initiates loading of the factory configuration into the Stratix or Stratix GX device. Factory configuration reads the remote configuration status register and determines the appropriate application configuration to load into the Stratix or Stratix GX device.
Page 507: Local Update Programming File Generation
Selecting Next Application from Factory Data The user watchdog timer in Stratix and Stratix GX devices ensures that an application configuration has loaded successfully and checks if the application configuration is operating correctly in user mode. The watchdog timer must be continually reset by the user logic. If an error...
Page 508 Open the Convert Programming Files window from the File menu. Select Programmer Object File (*.pof) from the drop-down list titled Programming File Type. 12–22 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 509 Remote System Configuration with Stratix & Stratix GX Devices Select the enhanced configuration device used (EPC4, EPC8, EPC16), and the mode used (1-bit Passive Serial or Fast Passive Parallel). Only during the initial programming file generation can you specify the Options, Configuration Device, or Mode settings.
Page 510 Configuration option bits and page 0 data occupy main flash sectors 0 through 4. See the Sharp LHF16J06 Flash memory used in EPC16 devices Data Sheet at www.altera.com to correlate memory addresses to the EPC16 flash sectors. In auto addressing mode, page 1 allocates all unused flash sectors.
Page 511 Lower unused memory address locations within the allotted region are filled with 1's. These filler bits are transmitted during a configuration cycle using page 1, but are ignored by the Stratix device. The memory map output file provides the exact byte address where real configuration data for page 1 begins.
Page 512 Save the CPF setup (optionally), by selecting Save Conversion Setup… and specifying a name for the COF output file. 10. Click OK to generate initial programming and memory map files. 12–26 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 513 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–14. CPF Setup for Initial Programming File Generation (Block Addressing) Altera Corporation 12–27 September 2004 Stratix Device Handbook, Volume 2...
Page 514 Also note that the HEX data stored in the main data area uses absolute addressing. If relative addressing were to be used, the main data contents would be justified with the top (higher address locations) of the memory. 12–28 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 515 Remote System Configuration with Stratix & Stratix GX Devices The initial programming file (POF) can be converted to an Intel Hexadecimal format file (*.HEXOUT) using the Quartus II CPF utility. Figure 12–16. Figure 12–16. Converting POF Programming File to Intel HEX Format...
Page 516 Save the CPF setup (optionally), by selecting Save Conversion Setup… and specifying a name for the COF output file. 10. Click OK to generate initial programming and memory map files. 12–30 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 517 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–17. Local Update Partial Programming File Generation Altera Corporation 12–31 September 2004 Stratix Device Handbook, Volume 2...
Page 518: Remote Update Programming File Generation
The CPF utility accepts a HEX input file for the bottom and main data areas, and includes this data in the 12–32 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 519 Remote System Configuration with Stratix & Stratix GX Devices POF output file. However, this is only supported for initial programming file generation. Partial programming file generation for updating user HEX data is not supported, but can be performed using the enhanced configuration device external flash interface.
Page 520 Setup… and specifying a name for the COF output file. Click OK to generate initial programming and memory map files. Figure 12–19. CPF Setup for Initial Programming File Generation (Auto Addressing) 12–34 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 521 Lower unused memory address locations within the allotted region are filled with 1's. These filler bits are transmitted during the application configuration cycle, but are ignored by the Stratix device. The memory map output file provides the exact byte address where real application configuration data for each page begins.
Page 522 Save the CPF setup (optionally), by selecting Save Conversion Setup… and specifying a name for the COF output file. 10. Click OK to generate initial programming and memory map files. 12–36 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 523 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–20. CPF Setup for Initial Programming File Generation (Block Addressing) Altera Corporation 12–37 September 2004 Stratix Device Handbook, Volume 2...
Page 524 (higher address locations) of the memory. The initial POF can be converted to an Intel Hexadecimal format file (*.HEXOUT) using the Quartus II CPF utility. See Figure 12–22. 12–38 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 525 Remote System Configuration with Stratix & Stratix GX Devices Figure 12–22. Converting POF Programming File to Intel HEX Format Partial Programming File Generation In remote update mode, the Quartus II CPF utility allows an existing application configuration page to be replaced with new data, or a new application configuration to be added.
Page 526 Difference File drop-down menu. You can select between an Intel HEX, JAM, JBC, and POF output file types. The output file name is the same as the POF output file name with a _dif suffix. 12–40 Altera Corporation Stratix Device Handbook, Volume 2 September 2004...
Page 527 Remote System Configuration with Stratix & Stratix GX Devices Save the CPF setup (optionally), by selecting Save Conversion Setup… and specifying a name for the COF output file. 10. Click OK to generate initial programming and memory map files. Figure 12–23. Remote Update Partial Programming File Generation Altera Corporation 12–41...
Page 528: Combining Max Devices & Flash Memory
0x0001003F PAGE 3 0x0012FFFA 0x00174EB4 Combining MAX This section describes remote system configuration with the Stratix or Stratix GX device and the Nios embedded processor, using a combination Devices & Flash of MAX devices and flash memory. ® Memory You can use MAX 3000 or MAX 7000 devices and an industry-standard flash memory device instead of enhanced configuration devices.
Page 529: Using An External Processor
The Nios embedded processor initiates loading of factory configuration into the Stratix or Stratix GX device. Figure 12–25 shows remote system configuration using a MAX device and flash memory combination.
Page 530: Conclusion
Stratix and Stratix GX devices are the first PLDs with dedicated support for remote system configuration. By allowing real-time system upgrades from a remote source, you can use Stratix and Stratix GX devices in a variety of applications that require automatic configuration updates.
Page 531: Section Vii. Pcb Layout Guidelines
Changed from Chapter 8, Volume 3 to Chapter 13, Volume 2. ● Corrected spelling error. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. January 2005, v1.2 ● This chapter was formerly chapter 15. September 2004, v1.1 ●...
Page 532 PCB Layout Guidelines Stratix Device Handbook, Volume 2 Section VII–2 Altera Corporation...
Page 533: Chapter 13. Package Information For Stratix Devices
Altera Stratix devices are available in BGA, FineLine BGA and Ultra FineLine BGA packages. Package Cross Reference Table 13–1. Stratix Devices in BGA, FineLine BGA & Ultra FineLine BGA Packages (Part 1 of 2) Device Package Pins EP1S10...
Page 534: Thermal Resistance
Thermal Resistance Table 13–1. Stratix Devices in BGA, FineLine BGA & Ultra FineLine BGA Packages (Part 2 of 2) Device Package Pins EP1S40 Flip-chip FineLine BGA Flip-chip BGA Flip-chip FineLine BGA 1,020 Flip-chip FineLine BGA 1,508 EP1S60 Flip-chip BGA Flip-chip FineLine BGA...
Page 535: Package Outlines
Package Information for Stratix Devices Table 13–2. Thermal Resistance of Stratix Devices (Part 2 of 2) θ (° C/W) θ θ θ θ (° C/W) (° C/W) (° C/W) (° C/W) Device Pin Count Package Still Air 100 ft./min. 200 ft./min.
Page 536: 484-Pin Fineline Bga - Flip Chip
Table 13–4. 484-Pin FineLine BGA Package Outline Dimensions Millimeter Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 23.00 BSC 23.00 BSC 0.50 0.60 0.70 1.00 BSC 13–4 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 537 Package Information for Stratix Devices Figure 13–1 shows a package outline for the 484-pin FineLine BGA packaging. Figure 13–1. 484-Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner Pin A1 ID Altera Corporation 13–5 July 2005 Stratix Device Handbook, Volume 2...
Page 538: 672-Pin Fineline Bga - Flip Chip
Table 13–6. 672-Pin FineLine BGA Package Outline Dimensions Millimeters Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 27.00 BSC 27.00 BSC 0.50 0.60 0.70 1.00 BSC 13–6 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 539 Package Information for Stratix Devices Figure 13–2 shows a package outline for the 672-pin FineLine BGA packaging. Figure 13–2. 672-Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner Pin A1 ID Altera Corporation 13–7 July 2005 Stratix Device Handbook, Volume 2...
Page 540: 780-Pin Fineline Bga - Flip Chip
Table 13–8. 780-Pin FineLine BGA Package Outline Dimensions Millimeters Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 29.00 BSC 29.00 BSC 0.50 0.60 0.70 1.00 BSC 13–8 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 541 Package Information for Stratix Devices Figure 13–3 shows a package outline for the 780-pin FineLine BGA packaging. Figure 13–3. 780-Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner Pin A1 ID Altera Corporation 13–9 July 2005 Stratix Device Handbook, Volume 2...
Page 542: 956-Pin Ball Grid Array (Bga) - Flip Chip
Table 13–10. 956-Pin BGA Package Outline Dimensions Millimeters Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 40.00 BSC 40.00 BSC 0.60 0.75 0.90 1.27 BSC 13–10 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 543 Package Information for Stratix Devices Figure 13–4 shows a package outline for the 956-pin BGA packaging. Figure 13–4. 956-Pin BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner 31 29 27 25 23 21 19 17 15 13 11 9...
Page 544: 1,020-Pin Fineline Bga - Flip Chip
Table 13–12. 1,020-Pin FineLine BGA Package Outline Dimensions Millimeters Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 33.00 BSC 33.00 BSC 0.50 0.60 0.70 1.00 BSC 13–12 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 545 Package Information for Stratix Devices Figure 13–5 shows a package outline for the 1,020-pin FineLine BGA packaging. Figure 13–5. 1,020-Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner Pin A1 ID Altera Corporation 13–13 July 2005 Stratix Device Handbook, Volume 2...
Page 546: 1,508-Pin Fineline Bga - Flip Chip
Table 13–14. 1,508-Pin FineLine BGA Package Outline Dimensions Millimeters Symbol Min. Nom. Max. – – 3.50 0.30 – – 0.25 – 3.00 – – 2.50 40.00 BSC 40.00 BSC 0.50 0.60 0.70 1.00 BSC 13–14 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 547 Package Information for Stratix Devices Figure 13–6 shows a package outline for the 1,508-pin FineLine BGA packaging. Figure 13–6. 1,508-Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW Pin A1 Corner Pin A1 ID Altera Corporation 13–15 July 2005 Stratix Device Handbook, Volume 2...
Page 548 Package Outlines 13–16 Altera Corporation Stratix Device Handbook, Volume 2 July 2005...
Page 549: Chapter 14. Designing With 1.5-V Devices
Once the device reaches operating conditions and is configured, Cyclone FPGAs operate as specified by the user. See the Stratix FPGA Family Data Sheet and the Cyclone FPGA Family Data Sheet for more information. Altera Corporation 14–1...
Page 550: Using Multivolt I/O Pins
= 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs. CCIO When V = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs. CCIO 14–2 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 551: Voltage Regulators
There are several companies that provide voltage regulators for low-voltage devices, such as Linear Technology Corporation, Maxim Integrated Products, Intersil Corporation (Elantec), and National Semiconductor Corporation. Altera Corporation 14–3 January 2005 Stratix Device Handbook, Volume 2...
Page 552 Stability The dominant pole placed by the output capacitor influences stability. Voltage regulator vendors can assist you in output capacitor selection for regulator designs that differ from what is offered. 14–4 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 553: Linear Voltage Regulators
There are two types of linear regulators available: one using a series pass element and another using a shunt element (e.g., a zener diode). Altera recommends using series linear regulators because shunt regulators are less efficient.
Page 554 1.5 V Adjustable-output regulators contain a voltage divider network that controls the regulator’s output. Figure 14–4 shows how you can also use a three-terminal linear regulator in an adjustable-output configuration. 14–6 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 555: Switching Voltage Regulators
There are two types of switching regulators, asynchronous and synchronous. Asynchronous switching regulators have one field effect transistor (FET) and a diode to provide the current path while the FET is off (see Figure 14–5). Altera Corporation 14–7 January 2005 Stratix Device Handbook, Volume 2...
Page 556: Maximum Output Current
For gate-drive voltages less than 9-V, use a logic-level MOSFET. A logic-level MOSFET is only required for topologies with a controller IC and an external MOSFET. 14–8 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 557: Selecting Voltage Regulators
Once you identify the design requirements, select the voltage regulator that is best for your design. Tables 14–5 14–6 list a few Linear Technology and Elantec regulators available at the time this document Altera Corporation 14–9 January 2005 Stratix Device Handbook, Volume 2...
Page 558: Voltage Divider Network
1.5-V power supply. See the voltage regulator data sheet to find detailed specifications. If you require further information that is not shown in the data sheet, contact the regulator’s vendor. 14–10 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 559 0.5-μF capacitor for 100-ms time out at room temperature. TIME is an AVX 15-μF/10-V surface-mount tantalum capacitor. Use adjustable 5.0- to 1.5-V regulators (shown in Figures 14–8 through 14–10) for 3.0- to 7.5-A low-cost, low-device-count, board-space-efficient solutions. Altera Corporation 14–11 January 2005 Stratix Device Handbook, Volume 2...
Page 560 This capacitor is necessary to maintain the voltage level at the input regulator. There could be a voltage drop at the input if the voltage supply is too far away. 14–12 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 561 0.1 μF 10 μF 0.33 μF MBR0530 0.01 μF 220 pF Notes to Figure 14–11: MBR0530 is a Motorola device. IRF7801 is a International Rectifier device. See the Panasonic 12TS-1R2HL device. Altera Corporation 14–13 January 2005 Stratix Device Handbook, Volume 2...
Page 562 10 kΩ ×2 OSENSE 1/2 FDS8936A 4.7 μF PGND OPEN PROG Notes to Figure 14–12: This is a KEMETT495X156M035AS capacitor. This is a Sumida CDRH127-6R1 inductor. This is a KEMETT510X687K004AS capacitor. 14–14 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 563 0.1 μF 0.1 μF 270 pF COSC 539 Ω 39 kΩ PGND 1 kΩ 10 μH 10 μF PGND 1.5 V Ceramic 0.1 μF 47 μF 5.0 V PGND EL7551C Altera Corporation 14–15 January 2005 Stratix Device Handbook, Volume 2...
Page 564 22 Ω 0.22 μF 2.2 nF 0.22 μF 4.7 μH PGND 1.5 V PGND 100 pF 539 Ω 330 μF 330 μF PGND 5.0 V PGND 1 kΩ PGND EL7564CM 14–16 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 565 These capacitors are ceramic or tantalum capacitor. These are BAT54S fast diodes. D4 is only required for EL7556ACM. This is a Sprague 293D337X96R3 2X330μF capacitor. This is a Sprague 293D337X96R3 3X330μF capacitor. Altera Corporation 14–17 January 2005 Stratix Device Handbook, Volume 2...
Page 566 0.22 μF 0.22 μF 0.1 μF 0.22 μF PGND 2.5 μH 330 μF PGND 1.5 V PGND 2.2 nF 3.3 V 330 μF 513 Ω PGND PGND 1 kΩ EL7563CM 14–18 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 567: V Regulator Application Examples
An example is shown to illustrate the voltage regulator selection process. Altera Corporation 14–19 January 2005 Stratix Device Handbook, Volume 2...
Page 568: Synchronous Switching Regulator Example
Use Cyclone Power Calculator (not applicable in this example because V = 3.3 V) C C I O Total user-mode current consumption = 620 mA C C I N T C C I O 14–20 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 569: Board Layout
Altera recommends that you use separate layers for signals, the ground plane, and voltage supply planes. You can support separate layers by using multi-layer PCBs, assuming you are using two signal layers.
Page 570 Figure 14–19. Single Regulator Solution for Systems that Require 5.0-V, 2.5-V & 1.5-V Supply Levels 1.5-V Device 1.5 V Altera 5.0 V Regulator Cyclone 2.5 V FPGA 2.5-V Device 14–22 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...
Page 571: Split-Plane Method
One plane split between 5.0-V and 1.5-V This technique assumes that the majority of devices are 2.5-V. To support MultiVolt I/O, Altera devices must have access to 1.5-V and 2.5-V planes. Figure 14–20. Split Board Layout for 2.5-V Systems With 5.0-V & 1.5-V Devices 5.0 V...
Page 572: References
Intersil Corporation. EL7562C Data Sheet (Monolithic 2 Amp DC:DC Step- Down Regulator). Milpitas: Intersil Corporation, 2002. Intersil Corporation. EL7563C Data Sheet (Monolithic 4 Amp DC:DC Step- Down Regulator). Milpitas: Intersil Corporation, 2002. 14–24 Altera Corporation Stratix Device Handbook, Volume 2 January 2005...