Page 1 January Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.8...
Page 2 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 3: Table Of Contents
Ordering Information ..............1–19 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Logic Array Blocks .
Page 4 Stratix IV Operational Mode Descriptions ........
Page 5 Stratix IV PLL Hardware Overview ........
Page 6 Mixing Voltage-Referenced and Non-Voltage-Referenced Standards ..... 6–47 Chapter 7. External Memory Interfaces in Stratix IV Devices Stratix IV Device Handbook...
Page 7 Stratix IV External Memory Interface Features ........
Page 8 Hot-Socketing Feature Implementation in Stratix IV Devices ........
Page 9 Stratix IV External Power Supply Requirements ........
Page 10 Contents Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 11: Chapter Revision Dates
Chapter Revision Dates The chapters in this document, Stratix IV Device Handbook, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Overview for the Stratix IV Device Family...
Page 12 Chapter Revision Dates Revised: February 2011 Part Number: SIV51012-3.2 Chapter 13. Power Management in Stratix IV Devices Revised: February 2011 Part Number: SIV51013-3.2 Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 13: Section I. Device Core
FPGA in the market place. This section includes the following chapters: ■ Chapter 1, Overview for the Stratix IV Device Family ■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices ■ Chapter 3, TriMatrix Embedded Memory Blocks in Stratix IV Devices ■...
Page 14 I–2 Section I: Device Core Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 15 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 16: Feature Summary
Feature Summary The following list summarizes the Stratix IV device family features: ■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively ■ Dedicated circuitry to support physical layer functionality for popular serial...
Page 17: Stratix Iv Gx Devices
Chapter 1: Overview for the Stratix IV Device Family 1–3 Feature Summary Stratix IV GX Devices Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps...
Page 18: Stratix Iv E Device
Chapter 1: Overview for the Stratix IV Device Family Feature Summary Stratix IV E Device Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive. Figure 1–2 shows a high-level Stratix IV E chip view.
Page 19: Stratix Iv Gt Devices
1–5 Feature Summary Stratix IV GT Devices Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps ■...
Page 20: Architecture Features
Architecture Features The Stratix IV device family features are divided into high-speed transceiver features and FPGA fabric and I/O features. The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT devices. High-Speed Transceiver Features The following sections describe high-speed transceiver features for Stratix IV GX and GT devices.
Page 21: Diagnostic Features
PCI Express Compiler User Guide. Signal Integrity Stratix IV devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. These enhancements include: Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis ■...
Page 22: Fpga Fabric And I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features. Device Core Features Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in ■ Stratix IV E devices, efficiently packed in unique and innovative adaptive logic modules (ALMs) ■...
Page 23: Plls
■ Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT devices DPA circuitry at the receiver automatically compensates for channel-to-channel ■...
Page 24: System Integration
For more information about how to connect the PLL, external memory interfaces, I/O, high-speed differential I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines and the Stratix IV GT Device Family Pin Connection Guidelines.
Page 25 Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part 1 of 2) Feature EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Package Option ALMs 29,040 42,240 70,300 91,200 116,480 141,440 212,480 72,600 105,600...
Page 26 (4) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (5) The difference between the Stratix IV GX devices in the –2 and –2x speed grades is the number of available transceiver channels. The –2 device allows you to use the transceiver CMU blocks as transceiver channels.
Page 27 On-package decoupling reduces the need for on-board or PCB decoupling capacitors by satisfying the transient current requirements at higher frequencies. The Power Delivery Network design tool for Stratix IV devices accounts for the on-package decoupling and reflects the reduced requirements for PCB decoupling capacitors.
Page 28 Table 1–3 lists the Stratix IV GX device on-package decoupling information. Table 1–3. Stratix IV GX Device On-Package Decoupling Information Ordering Information and V (Shared) CCIO CCL_GXB CCA_L/R EP4SGX70 HF35 21uF + 2470nF 10nF per bank 100nF per transceiver block 100nF 1470nF + 147nF per side...
Page 29 Table 1–4 lists the Stratix IV E device features. Table 1–4. Stratix IV E Device Features Feature EP4SE230 EP4SE360 EP4SE530 EP4SE820 Package Pin Count 1152 1152 1517 1760 1152 1517 1760 ALMs 91,200 141,440 212,480 325,220 228,000 353,600 531,200 813,050...
Page 30 For more information about decoupling design of engineering sample (ES) devices, contact Altera Technical Support. Table 1–7 lists the Stratix IV GT device features. Table 1–7. Stratix IV GT Device Features (Part 1 of 2) Feature EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3...
Page 31 Chapter 1: Overview for the Stratix IV Device Family 1–17 Architecture Features Table 1–7. Stratix IV GT Device Features (Part 2 of 2) Feature EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4 EP4S100G5 10G Transceiver Channels (600 Mbps - 11.3 Gbps with PMA + PCS)
Page 32 1–18 Chapter 1: Overview for the Stratix IV Device Family Architecture Features Table 1–8 lists the resource counts for the Stratix IV GT devices. Table 1–8. Stratix IV GT Device Package Options 1517 Pin 1932 Pin Device (40 mm x 40 mm)
Page 33: Integrated Software Platform
MegaWizard Plug-In Manager interface that guides you through configuration of the transceiver based on your application requirements. The Stratix IV GX and GT transceivers allow you to implement low-power and reliable high-speed serial interface applications with its fully reconfigurable hardware, optimal signal integrity, and integrated Quartus II software platform.
Page 34 1–20 Chapter 1: Overview for the Stratix IV Device Family Ordering Information Figure 1–5 shows the ordering codes for Stratix IV GT devices. Figure 1–5. Stratix IV GT Device Packaging Ordering Information EP4S EP4S Family S i g n a t u r e...
Page 35 Updated “FPGA Fabric and I/O Features” on page 1–8. ■ November 2008 Updated Table 1–1. ■ Updated Table 1–2. ■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT ■ Device.” on page 1–15. July 2008 Revised “Introduction”. May 2008 Initial release.
Page 36 1–22 Chapter 1: Overview for the Stratix IV Device Family Ordering Information Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 37: Logic Array Blocks
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 38 Either Side by Columns & LABs, & from Above by Rows The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB, as shown in Figure 2–2.
Page 39 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–3 Logic Array Blocks For more information about the MLAB, refer to the chapter. Figure 2–2. Stratix IV LAB and MLAB Structure LUT-based-64 x 1 Simple dual-port SRAM...
Page 40: Lab Interconnects
2–4 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Logic Array Blocks LAB Interconnects The LAB local interconnect can drive ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs/MLABs, M9K RAM blocks, M144K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB’s local interconnect through the...
Page 41: Adaptive Logic Modules
Adaptive Logic Modules The ALM is the basic building block of logic in the Stratix IV architecture. It provides advanced features with efficient logic usage. Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers.
Page 42 2–6 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain.
Page 43 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–7 Adaptive Logic Modules Figure 2–6 shows a detailed view of all the connections in an ALM. Figure 2–6. Stratix IV ALM Connection Details syncload aclr[1:0] carry_in...
Page 44: Alm Operating Modes
2–8 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT.
Page 45: Normal Mode
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one Stratix IV ALM, or a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
Page 46 Quartus II software to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically uses the full potential of the Stratix IV ALM. The Quartus II Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources.
Page 47: Extended Lut Mode
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–11 Adaptive Logic Modules Extended LUT Mode Use extended LUT mode to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs.
Page 48: Arithmetic Mode
2–12 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders.
Page 49 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–13 Adaptive Logic Modules Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared-arithmetic mode. The two-bit carry select feature in Stratix IV devices halves the propagation delay of carry chains within the ALM.
Page 50: Shared Arithmetic Mode
2–14 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add within the ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs.
Page 51: Lut-Register Mode
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–15 Adaptive Logic Modules Similar to the carry chains, the top and bottom halves of shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality.
Page 52 2–16 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Figure 2–13 shows the ALM in LUT-register mode. Figure 2–13. ALM in LUT-Register Mode with Three-Register Capability clk [2:0] aclr [1:0] reg_chain_in datain...
Page 53: Register Chain
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–17 Adaptive Logic Modules Register Chain In addition to general routing outputs, ALMs in the LAB have register-chain outputs. Register-chain routing allows registers in the same LAB to be cascaded together. The register-chain interconnect allows the LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift-register implementation.
Page 54: Alm Interconnects
2–18 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules ALM Interconnects There are three dedicated paths between the ALMs—register cascade, carry chain, and shared arithmetic chain. Stratix IV devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions.
Page 55: Lab Power Management Techniques
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–19 Adaptive Logic Modules LAB Power Management Techniques The following techniques are used to manage static and dynamic power consumption within the LAB: ■ To save AC power, the Quartus II software forces all adder inputs low when ALM adders are not in use.
Page 56 2–20 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Adaptive Logic Modules Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 57: Chapter 3. Trimatrix Embedded Memory Blocks In Stratix Iv Devices
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 58 3–2 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview Table 3–1. Summary of TriMatrix Memory Features (Part 2 of 2) Feature MLABs M9K Blocks M144K Blocks 8K × 1 16K × 8 4K × 2 64 × 8 16K ×...
Page 59: Trimatrix Memory Block Types
3–3 Overview Table 3–2 lists the capacity and distribution of the TriMatrix memory blocks in each Stratix IV family member. Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices Total Dedicated RAM Bits Total RAM Bits M144K Device...
Page 60 3–4 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview The default value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. The byte enable registers have no clear port.
Page 61: Packed Mode Support
3–5 Overview Packed Mode Support Stratix IV M9K and M144K blocks support packed mode. The packed mode feature packs two independent single-port RAMs into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block into true dual-port mode and using the MSB of the address to distinguish between the two logical RAMs.
Page 62: Address Clock Enable Support
Overview Address Clock Enable Support All Stratix IV memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable.
Page 63: Mixed Width Support
MLABs do not support mixed-width FIFO mode. Asynchronous Clear Stratix IV TriMatrix memory blocks support asynchronous clears on output latches and output registers. Therefore, if your RAM is not using output registers, you can still clear the RAM outputs using the output latch asynchronous clear.
Page 64: Error Correction Code (Ecc) Support
Overview Error Correction Code (ECC) Support Stratix IV M144K blocks have built-in support for error correction code (ECC) when in ×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in the memory array. The M144K blocks have a single-error-correction double-error-detection (SECDED) implementation.
Page 65: Memory Modes
Block Data Output Memory Modes Stratix IV TriMatrix memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations.
Page 66: Single-Port Ram Mode
3–10 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Single-Port RAM Mode All TriMatrix memory blocks support single-port mode. Single-port mode allows you to do either one-read or one-write operation at a time. Simultaneous reads and writes are not supported in single-port mode.
Page 67: Simple Dual-Port Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–11 Memory Modes Figure 3–8 shows timing waveforms for read and write operations in single-port mode with unregistered outputs. Registering the RAM’s outputs simply delays the q output by one clock cycle.
Page 68 3–12 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2) Write Port Read Port 8K × 1 4K × 2 2K × 4 1K × 8 512 ×...
Page 69 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–13 Memory Modes Figure 3–10 shows timing waveforms for read and write operations in simple dual-port mode with unregistered outputs. Registering the RAM outputs simply delays the q output by one clock cycle.
Page 70: True Dual-Port Mode
Memory Modes True Dual-Port Mode Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
Page 71 This results in unknown data being stored to that address location. No conflict resolution circuitry is built into the Stratix IV TriMatrix memory blocks. You must handle address conflicts external to the RAM block.
Page 72: Shift-Register Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Memory Modes Shift-Register Mode All Stratix IV memory blocks support shift register mode. Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions.
Page 73: Rom Mode
Clocking Modes ROM Mode All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the ROM contents of these blocks. The address lines of the ROM are registered on M9K and M144K blocks, but can be unregistered on MLABs. The outputs can be registered or unregistered.
Page 74: Independent Clock Mode
Design Considerations Independent Clock Mode Stratix IV TriMatrix memory blocks can implement independent clock mode for true dual-port memories. In this mode, a separate clock is available for each port (clock A and clock B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.
Page 75: Conflict Resolution
Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Read-During-Write Behavior You can customize the read-during-write behavior of the Stratix IV TriMatrix memory blocks to suit your design needs. Two types of read-during-write operations are available: same port and mixed port.
Page 76 3–20 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Design Considerations Figure 3–16 shows sample functional waveforms of same-port read-during-write behavior in don’t care mode for MLABs. Figure 3–16. MLABs Same-Port Read-During Write: Don’t Care Mode clk_a address...
Page 77: Mixed-Port Read-During-Write Mode
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–21 Design Considerations Figure 3–18 shows sample functional waveforms of same-port read-during-write behavior in old data mode for M9K and M144K blocks. Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode...
Page 78 3–22 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Design Considerations Figure 3–20 shows a sample functional waveform of mixed-port read-during-write behavior for don’t care mode in MLABs. Figure 3–20. MLABs Mixed-Port Read-During-Write: Don’t Care Mode clk_a wraddress...
Page 79: Power-Up Conditions And Memory Initialization
You must take this into consideration when designing logic that might evaluate the initial power-up values of the MLAB memory block. For Stratix IV devices, the Quartus II software initializes the RAM cells to zero unless there is a .mif file specified.
Page 80: Power Management
Design Considerations Power Management Stratix IV memory block clock-enables allow you to control clocking of each memory block to reduce AC power consumption. Use the read-enable signal to ensure that read operations only occur when you need them to. If your design does not need...
Page 81 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 82: Chapter 4. Dsp Blocks In Stratix Iv Devices
Stratix IV DSP Block Overview Stratix IV DSP Block Overview Each Stratix IV device has two to seven columns of DSP blocks that implement multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift functions efficiently. Architectural highlights of the Stratix IV DSP block include: ■...
Page 83 Chapter 4: DSP Blocks in Stratix IV Devices 4–3 Stratix IV DSP Block Overview Table 4–1. Number of DSP Blocks in Stratix IV Devices (Part 2 of 2) Four High-Precision Multiplier Independent Input and Output Multiplication Operators Multiplier Adder Adder Mode...
Page 84: Stratix Iv Simplified Dsp Operation
Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation Stratix IV Simplified DSP Operation In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in Equation 4–1 Figure 4–2.
Page 85 Chapter 4: DSP Blocks in Stratix IV Devices 4–5 Stratix IV Simplified DSP Operation Following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the alternative functions per half block, as shown in Equation 4–2...
Page 86 To support commonly found FIR-like structures efficiently, a major addition to the DSP block in Stratix IV devices is the ability to propagate the result of one half block to the next half block completely within the DSP block without additional soft logic overhead.
Page 87 4–7 Stratix IV Simplified DSP Operation Figure 4–5 shows a top-level view of the Stratix IV DSP block. Figure 4–6 on page 4–9 shows a more detailed top-level view of the DSP block. Figure 4–5. Stratix IV Full DSP Block...
Page 88: Stratix Iv Operational Modes Overview
Stratix IV Operational Modes Overview Stratix IV Operational Modes Overview You can use each Stratix IV DSP block in one of five basic operational modes. Table 4–2 lists the five basic operational modes and the number of multipliers that you can implement within a single DSP block, depending on the mode.
Page 89: Stratix Iv Dsp Block Resource Descriptions
Chapter 4: DSP Blocks in Stratix IV Devices 4–9 Stratix IV DSP Block Resource Descriptions Stratix IV DSP Block Resource Descriptions The DSP block consists of the following elements: ■ Input register bank ■ Four two-multiplier adders Pipeline register bank ■...
Page 90: Input Registers
4–10 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions Input Registers All of the DSP block registers are triggered by the positive edge of the clock signal and are cleared after power up. Each multiplier operand can feed an input register or go directly to the multiplier, bypassing the input registers.
Page 91 Chapter 4: DSP Blocks in Stratix IV Devices 4–11 Stratix IV DSP Block Resource Descriptions A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) can be driven from general routing or from the cascade...
Page 92: Multiplier And First-Stage Adder
(LE) resources required, avoids routing congestion, and results in predictable timing. The first multiplier in every half DSP block (top- and bottom-half) in Stratix IV devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure 4–6 on page...
Page 93: Pipeline Register Stage
Chapter 4: DSP Blocks in Stratix IV Devices 4–13 Stratix IV DSP Block Resource Descriptions Each half block has its own signa and signb signal. Therefore, all of the data A inputs feeding the same half DSP block must have the same sign representation. Similarly, all of the data B inputs feeding the same half DSP block must have the same sign representation.
Page 94: Rounding And Saturation Stage
72-bit banks to support 36 × 36 output results. The outputs of the different stages in the Stratix IV devices are routed to the output registers through an output selection unit. Depending on the operational mode of the...
Page 95: Stratix Iv Operational Mode Descriptions
■ aclr[3..0] Stratix IV Operational Mode Descriptions This section contains an explanation of different operational modes in Stratix IV devices. Independent Multiplier Modes In independent input and output multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers.
Page 96 4–16 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–8. 18-Bit Independent Multiplier Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round overflow (1) aclr[3..0] output_saturate dataa_0[17..0] result_0[ ] datab_0[17..0] dataa_1[17..0] result_1[ ] datab_1[17..0]...
Page 97 Chapter 4: DSP Blocks in Stratix IV Devices 4–17 Stratix IV Operational Mode Descriptions Figure 4–9. 12-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[11..0] result_0[ ] datab_0[11..0] dataa_1[11..0] result_1[ ] datab_1[11..0] dataa_2[11..0] result_2[ ] datab_2[11..0]...
Page 98 4–18 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–10. 9-Bit Independent Multiplier Mode Shown for a Half Block clock[3..0] signa ena[3..0] aclr[3..0] signb dataa_0[8..0] result_0[ ] datab_0[8..0] dataa_1[8..0] result_1[ ] datab_1[8..0] dataa_2[8..0] result_2[ ] datab_2[8..0]...
Page 99: 36-Bit Multiplier
DSP block and is implemented in the DSP block automatically by selecting 36 × 36 mode. Stratix IV devices can have up to two 36-bit multipliers per DSP block (one 36-bit multiplier per half DSP block). The...
Page 100: Double Multiplier
Stratix IV Operational Mode Descriptions Double Multiplier You can configure the Stratix IV DSP block to efficiently support a signed or unsigned 54 × 54-bit multiplier that is required to compute the mantissa portion of an IEEE double-precision floating point multiplication. You can build a 54 × 54-bit multiplier using basic 18 ×...
Page 101 Chapter 4: DSP Blocks in Stratix IV Devices 4–21 Stratix IV Operational Mode Descriptions Figure 4–13. Unsigned 54 × 54 Multiplier for a Half-DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] Two Multiplier "0" Adder Mode "0" dataa[53..36] datab[53..36] Double Mode dataa[35..18]...
Page 102: Two-Multiplier Adder Sum Mode
4–22 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Two-Multiplier Adder Sum Mode In a two-multiplier adder configuration, the DSP block can implement four 18-bit two-multiplier adders (2 two-multiplier adders per half DSP block). You can configure the adders to take the sum or difference of two multiplier outputs.
Page 103 Chapter 4: DSP Blocks in Stratix IV Devices 4–23 Stratix IV Operational Mode Descriptions Figure 4–14. Two-Multiplier Adder Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate overflow (1) dataa_0[17..0] datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0]...
Page 104: 18 X 18 Complex Multiply
4–24 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–15. Loopback Mode for a Half DSP Block signa clock[3..0] signb ena[3..0] output_round output_saturate aclr[3..0] zero_loopback overflow (1) dataa_0[17..0] loopback datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0]...
Page 105 Chapter 4: DSP Blocks in Stratix IV Devices 4–25 Stratix IV Operational Mode Descriptions To implement this complex multiplication within the DSP block, the real part ((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a ×...
Page 106: Four-Multiplier Adder
4–26 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Four-Multiplier Adder In the four-multiplier adder configuration shown in Figure 4–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block).
Page 107: High-Precision Multiplier Adder Mode
Chapter 4: DSP Blocks in Stratix IV Devices 4–27 Stratix IV Operational Mode Descriptions Four-multiplier adder mode supports the rounding and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block.
Page 108 4–28 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–18. High-Precision Multiplier Adder Configuration signa clock[3..0] signb ena[3..0] aclr[3..0] overflow (1) dataA[0:17] dataB[0:17] dataA[0:17] <<18 dataB[18:35] result[ ] dataC[0:17] dataD[0:17] dataC[0:17] <<18 dataD[18:35] Half-DSP Block...
Page 109: Multiply Accumulate Mode
Chapter 4: DSP Blocks in Stratix IV Devices 4–29 Stratix IV Operational Mode Descriptions Multiply Accumulate Mode In multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. The output of the DSP block is looped back to the...
Page 110: Shift Modes
32-bit rotator or barrel shifter, ROT[N] You can switch between these modes using the dynamic rotate and shift control signals. You can use shift mode in a Stratix IV device by using a soft embedded processor such ® as Nios II to perform the dynamic shift and rotate operation.
Page 111 Chapter 4: DSP Blocks in Stratix IV Devices 4–31 Stratix IV Operational Mode Descriptions Figure 4–20. Shift Operation Mode Shown for a Half DSP Block signa clock[3..0] signb ena[3..0] rotate shift_right aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0]...
Page 112: Rounding And Saturation Mode
Rounding and saturation functions are often required in DSP arithmetic. Use rounding to limit bit growth and its side effects; use saturation to reduce overflow and underflow side effects. Two rounding modes are supported in Stratix IV devices: ■ Round-to-nearest-integer mode ■...
Page 113 800000001h 800000000h Stratix IV devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0]) for the rounding and saturate logic unit, providing higher flexibility. These 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as...
Page 114: Dsp Block Control Signals
(A × B)]] DSP Block Control Signals The Stratix IV DSP block is configured using a set of static and dynamic signals. You can configure the DSP block dynamic signals. You can set the signals to toggle or not toggle at run time.
Page 115: Software Support
DSP block-wide asynchronous clear signals (active low). aclr2 aclr3 Total Count per Full Block Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design—instantiation and inference. Both methods use the following Quartus II megafunctions: ■ lpm_mult ■...
Page 116: Software Support
4–36 Chapter 4: DSP Blocks in Stratix IV Devices Software Support For more information, refer to the “Synthesis” section in volume 1 of the Quartus II Handbook. Document Revision History Table 4–10 lists the revision history for this chapter. Table 4–10. Document Revision History...
Page 117 Chapter 4: DSP Blocks in Stratix IV Devices 4–37 Software Support February 2011 Altera Corporation Stratix IV Device Handbook Volume 1...
Page 118 4–38 Chapter 4: DSP Blocks in Stratix IV Devices Software Support Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 119: Clock Networks In Stratix Iv Devices
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 120 Stratix IV devices have up to 32 dedicated single-ended clock pins or 16 dedicated differential clock pins (CLK[0..15]p and CLK[0..15]n) that can drive either the GCLK or RCLK networks. These clock pins are arranged on the four sides of the Stratix IV device, as shown in Figure 5–1...
Page 121: Global Clock Networks
Clock Networks in Stratix IV Devices Global Clock Networks Stratix IV devices provide up to 16 GCLKs that can drive throughout the device, serving as low-skew clock sources for functional blocks such as adaptive logic modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks, and PLLs.
Page 122: Regional Clock Networks
The Stratix IV device IOEs and internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals;...
Page 123 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–5 Clock Networks in Stratix IV Devices Figure 5–3. RCLK Networks (EP4S40G2, EP4S100G2, EP4SGX180, and EP4SGX230 Devices) CLK[12..15] RCLK[54..63] RCLK[44..53] RCLK[0..5] RCLK[38..43] Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31]...
Page 124: Periphery Clock Networks
(PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK networks. PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Stratix IV device. Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices) CLK[12..15]...
Page 125 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–7 Clock Networks in Stratix IV Devices Figure 5–6. PCLK Networks (EP4S40G2, EP4S100G2, EP4SE230, EP4SE360, EP4SGX180, EP4SGX230, EP4SGX290, and EP4SGX360 Devices) CLK[12..15] PCLK[0..10] PCLK[77..87] PCLK[11..21] PCLK[66..76] Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 PCLK[22..32]...
Page 126 5–8 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Figure 5–8. PCLK Networks (EP4SE820 Device) CLK[12..15] PCLK[0..15] PCLK[116..131] PCLK[16..32] PCLK[99..115] CLK[0..3] CLK[8..11] PCLK[33..49] PCLK[82..98] PCLK[50..65] PCLK[66..81] CLK[4..7] Stratix IV Device Handbook September 2012 Altera Corporation...
Page 127: Clock Sources Per Quadrant
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row. Clock Regions Stratix IV devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in the entire device. You can use these clock resources to form the following types of clock regions: ■...
Page 128: Clock Network Sources
Clock Network Sources In Stratix IV devices, clock input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks. For connectivity between dedicated pins CLK[0..15] and the GCLK and RCLK networks, refer to Table 5–2...
Page 129: Pll Clock Outputs
Table 5–3 lists the connectivity between the dedicated clock input pins and RCLKs in Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network. Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)
Page 130: Clock Input Connections To The Plls
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a global clock is used. (2) For the availability of the clock input pins in each device density, refer to the “Stratix IV Device Pin-Out Files” section of the...
Page 131: Clock Output Connections
I/O bank as the PLL used. Clock Output Connections PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK networks. For Stratix IV PLL connectivity to GCLK networks, refer to Table 5–5.
Page 132: Clock Control Block
5–14 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs (Part 2 of 2) PLL Number Clock Resource — — — —...
Page 133 (.sof or .pof) generated by the Quartus II software. You can power down the Stratix IV clock networks using both static and dynamic approaches. When a clock network is powered down, all the logic fed by the clock network is in off-state, thereby reducing the overall power consumption of the device.
Page 134 5–16 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.
Page 135: Clock Enable Signals
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof). In Stratix IV devices, the clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when you are not using a PLL.
Page 136: Clock Source Control For Plls
Clock Source Control for PLLs The clock input to Stratix IV PLLs comes from clock input multiplexers. The clock multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK and RCLK networks, or from dedicated connections between adjacent top/bottom and left/right PLLs.
Page 137: Cascading Plls
GCLK or RCLK network. Using this path reduces clock jitter when cascading PLLs. Stratix IV GX devices allow cascading the left and right PLLs to transceiver PLLs (CMU PLLs and receiver CDRs).
Page 138 — — EP4SGX530 F1760 F1932 All Stratix IV PLLs have the same core analog structure with only minor differences in the features that are supported. Table 5–8 lists the features of top/bottom and left/right PLLs in Stratix IV devices. Table 5–8. PLL Features in Stratix IV Devices (Part 1 of 2)
Page 139 (4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs. (5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix IV °...
Page 140 5–22 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Figure 5–18 shows the location of PLLs in Stratix IV devices. Figure 5–18. PLL Locations in Stratix IV Devices Top/Bottom PLLs Top/Bottom PLLs CLK[12..15]...
Page 141: Stratix Iv Pll Hardware Overview
There are a number of components that comprise a PLL to achieve this phase alignment. Stratix IV PLLs align the rising edge of the input reference clock to a feedback clock using the phase-frequency detector (PFD). The falling edges are determined by the duty-cycle specifications.
Page 142: Pll Clock I/O Pins
(1) The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs. (2) This is the VCO post-scale counter K. (3) The FBOUT port is fed by the M counter in Stratix IV PLLs. You can drive the GCLK or RCLK inputs using an output from another PLL, a...
Page 143 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–25 PLLs in Stratix IV Devices Figure 5–20 shows the clock I/O pins associated with the top and bottom PLLs. Figure 5–20. External Clock Outputs for Top and Bottom PLLs...
Page 144 I/O Features in Stratix IV Devices chapter. Stratix IV PLLs can also drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not need external PLL clocking.
Page 145: Pll Control Signals
Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL.
Page 146: Clock Feedback Modes
Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Clock Feedback Modes Stratix IV PLLs support up to six different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. Table 5–9 lists the clock feedback modes supported by the Stratix IV device PLLs.
Page 147: Source Synchronous Mode
IOE input register. Figure 5–22 shows an example waveform of the clock and data in this mode. Altera recommends source synchronous mode for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard.
Page 148: Source-Synchronous Mode For Lvds Compensation
5–30 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Source-Synchronous Mode for LVDS Compensation The goal of source-synchronous mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180°...
Page 149: Normal Mode
ZDB mode is supported on all Stratix IV PLLs. When using Stratix IV PLLs in ZDB mode, along with single-ended I/O standards, to ensure phase alignment between the CLK pin and the external clock output (CLKOUT) pin, you must instantiate a bi-directional I/O pin in the design to serve as the feedback path connecting the FBOUT and FBIN ports of the PLL.
Page 150: External Feedback Mode
5–32 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices When using ZDB mode, to avoid signal reflection, do not place board traces on the bi-directional I/O pin. Figure 5–26. ZDB Mode in Stratix IV PLLs inclk ÷n...
Page 151: Clock Multiplication And Division
Clock Multiplication and Division Each Stratix IV PLL provides clock synthesis for PLL output ports using M/(N* post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match f (M/N).
Page 152: Post-Scale Counter Cascading
ALTPLL megafunction. Post-Scale Counter Cascading Stratix IV PLLs support post-scale counter cascading to create counters larger than 512. This is automatically implemented in the Quartus II software by feeding the output of one C counter into the input of the next C counter, as shown in Figure 5–30.
Page 153: Programmable Duty Cycle
(PVT). You can phase-shift the output clocks from the Stratix IV PLLs in either of these two resolutions: Fine resolution using VCO phase taps ■...
Page 154 CLK1 d0-2 CLK2 You can use coarse- and fine-phase shifts to implement clock delays in Stratix IV devices. Stratix IV devices support dynamic phase-shifting of VCO phase taps only. You can reconfigure the phase shift any number of times. Each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly.
Page 155: Programmable Bandwidth
5–37 PLLs in Stratix IV Devices Programmable Bandwidth Stratix IV PLLs provide advanced control of the PLL bandwidth using the PLL loop’s programmable characteristics, including loop filter and charge pump. Background PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter.
Page 156: Implementation
PLL output. A low-bandwidth PLL filters out reference clock jitter but increases lock time. Stratix IV PLLs allow you to control the bandwidth over a finite range to customize the PLL characteristics for a particular application.
Page 157: Spread-Spectrum Tracking
However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the PLL. Stratix IV PLLs can track a spread-spectrum input clock as long as it is within input-jitter tolerance specifications. Stratix IV devices cannot internally generate spread-spectrum clocks.
Page 158: Automatic Clock Switchover
PLL may lose lock after the switchover is completed and needs time to re-lock. Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.
Page 159 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–41 PLLs in Stratix IV Devices In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. When they are asserted, the clock sense block has detected that the corresponding clock input has stopped toggling.
Page 160 5–42 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Figure 5–36 shows a clock switchover waveform controlled by clkswitch. In this case, both clock sources are functional and inclk0 is selected as the reference clock;...
Page 161: Manual Clock Switchover
For more information about PLL software support in the Quartus II software, refer to Phase-Locked Loop (ALTPLL) Megafunction User Guide. Guidelines When implementing clock switchover in Stratix IV PLLs, use the following guidelines: ■ Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 100% (2×) of each other.
Page 162: Pll Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In Stratix IV PLLs, you can reconfigure both the counter settings and phase-shift the PLL output clock in real time. You can also change the charge pump and loop-filter components, which dynamically affects PLL bandwidth.
Page 163: Pll Reconfiguration Hardware Implementation
Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–45 PLLs in Stratix IV Devices PLL Reconfiguration Hardware Implementation The following PLL components are reconfigurable in real time: Pre-scale counter (n) ■ ■ Feedback counter (m) ■ Post-scale output counters (C0 - C9) ■...
Page 164 5–46 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Table 5–10 lists how these signals can be driven by the PLD logic array or I/O pins. Table 5–10. Real-Time PLL Reconfiguration Ports PLL Port Name...
Page 165: Post-Scale Counters (C0 To C9)
Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–47 PLLs in Stratix IV Devices Figure 5–40 shows a functional simulation of the PLL reconfiguration feature. Figure 5–40. PLL Reconfiguration Waveform (LSB) (MSB) SCANDATA SCANCLK SCANCLKENA D0_old Dn_old SCANDATAOUT...
Page 166: Scan Chain Description
■ Scan Chain Description The length of the scan chain varies for different Stratix IV PLLs. The top and bottom PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right PLLs have seven post-scale counters and a 180-bit scan chain.
Page 167 (1) Left and right PLLs have the same scan-chain order. The post-scale counters end at C6. Figure 5–42 shows the scan-chain bit-order sequence for post-scale counters in all Stratix IV PLLs. Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs DATAIN rbypass DATAOUT...
Page 168: Charge Pump And Loop Filter
Stratix IV PLLs. Table 5–12. Charge Pump Current Bit Settings CP[2] CP[1] CP[0] Decimal Value for Setting Table 5–13 lists the possible settings for loop-filter resistor (R) values for Stratix IV PLLs. Table 5–13. Loop-Filter Resistor Bit Settings LFR[4] LFR[3] LFR[2] LFR[1]...
Page 169: Bypassing A Pll
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9 counters) factor of one. Table 5–15 lists the settings for bypassing the counters in Stratix IV PLLs. Table 5–15. PLL Counter Settings PLL Scan Chain Bits [0..8] Settings...
Page 170 5–52 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Table 5–16. Dynamic Phase-Shifting Control Signals (Part 2 of 2) Signal Name Description Source Destination Free running clock from the core used in combination with PHASESTEP to...
Page 171 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–53 PLLs in Stratix IV Devices You can repeat dynamic phase-shifting indefinitely. For example, in a design where the VCO frequency is set to 1000 MHz and the output clock frequency is 100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180°, which is a phase shift of 5 ns.
Page 172: Pll Specifications
■ Minor text edits. ■ Updated Table 5–1 and Table 5–7. ■ Updated “Clock Networks in Stratix IV Devices”, “Periphery Clock Networks”, and ■ “Cascading PLLs” sections. Added Figure 5–5, Figure 5–6, Figure 5–7, Figure 5–8, and Figure 5–9. ■...
Page 173 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 5–55 PLLs in Stratix IV Devices Table 5–18. Document Revision History (Part 2 of 2) Date Version Changes Updated Table 5–1 and Table 5–7. ■ April 2009 Updated Figure 5–3 and Figure 5–4.
Page 174 5–56 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 175 ■ Chapter 7, External Memory Interfaces in Stratix IV Devices ■ Chapter 8, High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Page 176 II–2 Section II: I/O Interfaces Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 177 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 178: I/O Standards Support
I/O standards Stratix IV devices support, as well as the typical applications. These devices support V voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V. CCIO Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2) I/O Standard Application 3.3-V LVTTL/LVCMOS General purpose 2.5-V LVCMOS...
Page 179: I/O Standards And Voltage Levels
6–1: (1) The 3.3-V LVTTL/LVCMOS standard is supported using V at 3.0 V. CCIO (2) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19. For more information about transceiver supported I/O standards, refer to the Transceiver Architecture in Stratix IV Devices chapter.
Page 180 6–4 Chapter 6: I/O Features in Stratix IV Devices I/O Standards Support Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (Part 2 of 3) CCIO CCPD Standard Input Operation Output Operation (Board I/O Standard (Pre-Driver (Input Ref...
Page 181: I/O Banks
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without on-chip R support. (3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19.
Page 182 6–6 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–1. Stratix IV E Devices I/0 Banks Bank 8A Bank 8B Bank 7B Bank 8C Bank 7C Bank 7A I/O banks 8A, 8B, and 8C support all I/O banks 7A, 7B, and 7C support all...
Page 183 It is a graphical representation only. (9) Stratix IV devices do not support the PCI clamp diode when V is 1.2 V, 1.5 V, or 1.8 V.
Page 184: Modular I/O Banks
I/O pins available in each I/O bank. In Stratix IV devices, the maximum number of I/O banks per side is either four or six, depending on the device density. When migrating between devices with a different number of I/O banks per side, it is the middle or “B”...
Page 185 Chapter 6: I/O Features in Stratix IV Devices 6–9 I/O Banks Figure 6–4 through Figure 6–16 show the number of I/O pins and packaging information for different sets of available devices. They show the top view of the silicon die that corresponds to a reverse view for flip chip packages. They are graphical representations only.
Page 186 6–10 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–6. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1517-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A Bank 6B...
Page 187 Chapter 6: I/O Features in Stratix IV Devices 6–11 I/O Banks Figure 6–8. Number of I/Os in Each Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin FineLine BGA Package Number of Number Transceiver of I/Os Channels Bank...
Page 188 6–12 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–10. Number of I/Os in Each Bank in EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A Bank 1C...
Page 189 Chapter 6: I/O Features in Stratix IV Devices 6–13 I/O Banks Figure 6–12. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A...
Page 190 6–14 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Figure 6–13. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A...
Page 191 Chapter 6: I/O Features in Stratix IV Devices 6–15 I/O Banks Figure 6–14. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine BGA Package Number of I/Os Bank Name Bank 1A Bank 6A...
Page 192 6–16 Chapter 6: I/O Features in Stratix IV Devices I/O Banks The information in Figure 6–15 Figure 6–16 applies to Stratix IV GX and GT devices. Figure 6–15. Number of I/Os in Each Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine...
Page 193: I/O Structure
(1) There are two additional PMA-only transceiver channels in each transceiver bank. I/O Structure The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate or DDR transfer.
Page 194 6–18 Chapter 6: I/O Features in Stratix IV Devices I/O Structure ■ On-chip series termination without calibration ■ On-chip parallel termination with calibration On-chip differential termination ■ ■ PCI clamping diode I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (OE) path for handling the OE signal to the output buffer.
Page 195: V I/O Interface
When using the Stratix IV device as a transmitter, you can use slow slew rate and series termination to limit overshoot and undershoot at the I/O pins, but they are not required.
Page 196: High-Speed Differential I/O With Dpa Support
Programmable Current Strength The output buffer for each Stratix IV device I/O pin has a programmable current strength control for certain I/O standards. Use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane.
Page 197: Programmable Slew Rate Control
Programmable Slew Rate Control The output buffer for each Stratix IV device regular- and dual-function I/O pin has a programmable output slew-rate control that you can configure for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems.
Page 198: Programmable I/O Delay
High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices chapter. Programmable Output Buffer Delay Stratix IV devices support delay chains built inside the single-ended output buffer, as shown in Figure 6–17 on page 6–18. The delay chains can independently control the...
Page 199: Programmable Pull-Up Resistor
Interfaces and DPA in Stratix IV Devices chapter. MultiVolt I/O Interface The Stratix IV architecture supports the MultiVolt I/O interface feature that allows the Stratix IV devices in all packages to interface with systems of different supply voltages. You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply, depending on the output requirements.
Page 200: On-Chip Termination Support And I/O Termination Schemes
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use an internal clamping diode for column I/O pins.
Page 201 Stratix IV devices support driver-impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce reflections. Stratix IV devices support on-chip series termination for single-ended I/O standards (Figure 6–18).
Page 202: On-Chip Series Termination With Calibration
On-Chip Termination Support and I/O Termination Schemes On-Chip Series Termination with Calibration Stratix IV devices support on-chip series termination with calibration in all banks. The on-chip series termination calibration circuit compares the total impedance of the I/O buffer to the external 25-  ±1% or 50-  ±1% resistors connected to the RUP and RDN pins and dynamically enables or disables the transistors until they match.
Page 203: Left-Shift Series Termination Control
HSTL-12 Class II — Left-Shift Series Termination Control Stratix IV devices support left-shift series termination control. You can use left-shift series termination control to get the calibrated OCT R with half of the impedance value of the external reference resistors connected to the RUP and RDN pins. This feature is useful in applications that require both 25-...
Page 204: On-Chip Parallel Termination With Calibration
On-Chip Termination Support and I/O Termination Schemes On-Chip Parallel Termination with Calibration Stratix IV devices support on-chip parallel termination with calibration in all banks. On-chip parallel termination with calibration is only supported for input configuration of input and bidirectional pins. Output pin configurations do not support on-chip parallel termination with calibration.
Page 205: Expanded On-Chip Series Termination With Calibration
HSTL-12 40–60 20–60 Dynamic On-Chip Termination Stratix IV devices support on and off dynamic termination, both series and parallel, for a bidirectional I/O in all I/O banks. Figure 6–21 shows the termination schemes supported in Stratix IV devices. Dynamic parallel termination is enabled only when the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Page 206 50  parallel OCT on the input buffer of a bidirectional pin and calibrated 40  series OCT on the output buffer because these would require two separate calibration blocks with different RUP and RDN resistor values. Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices VCCIO VCCIO Transmitter Receiver 100 Ω...
Page 207: Summary Of Oct Assignments
Chapter 6: I/O Features in Stratix IV Devices 6–31 On-Chip Termination Support and I/O Termination Schemes LVDS Input OCT (R Stratix IV devices support OCT for differential LVDS input buffers with a nominal resistance value of 100  , as shown in Figure 6–22. Differential OCT R...
Page 208: Oct Calibration
Table 6–10 lists the OCT calibration blocks in Banks 1A through 4C. Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 1 of 2) Bank Number of Device...
Page 209 Chapter 6: I/O Features in Stratix IV Devices 6–33 OCT Calibration Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 2 of 2) Bank Number of Device OCT Blocks — — — —...
Page 210: Sharing An Oct Calibration Block On Multiple I/O Banks
6–34 Chapter 6: I/O Features in Stratix IV Devices OCT Calibration Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 2 of 2) Bank Number of Device OCT Blocks — — — —...
Page 211: Oct Calibration Block Modes Of Operation
Chapter 6: I/O Features in Stratix IV Devices 6–35 OCT Calibration For example, Figure 6–23 shows a group of I/O banks that has the same V CCIO voltage. If a group of I/O banks has the same V voltage, you can use one OCT CCIO calibration block to calibrate the group of I/O banks placed around the periphery.
Page 212: User Mode
6–36 Chapter 6: I/O Features in Stratix IV Devices OCT Calibration User Mode In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to calibrate and serially transfer calibration codes from each OCT calibration block to any I/O.
Page 213: Oct Calibration
Chapter 6: I/O Features in Stratix IV Devices 6–37 OCT Calibration OCT Calibration Figure 6–25 shows user mode signal-timing waveforms. To calibrate OCT block[N] (where N is a calibration block number), you must assert ENAOCT one cycle before asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before the ENASER[N] signal is asserted.
Page 214: Example Of Using Multiple Oct Calibration Blocks
6–38 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Example of Using Multiple OCT Calibration Blocks Figure 6–26 shows a signal timing waveform for two OCT calibration blocks doing R and R calibration. Calibration blocks can start calibrating at different times by asserting the ENASER signals at different times.
Page 215 Chapter 6: I/O Features in Stratix IV Devices 6–39 Termination Schemes for I/O Standards In Stratix IV devices, you cannot use series and parallel OCT simultaneously. For more information, refer to “Dynamic On-Chip Termination” on page 6–29. Figure 6–27. SSTL I/O Standard Termination...
Page 216 6–40 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Figure 6–28. HSTL I/O Standard Termination HSTL Class II Termination HSTL Class I V TT V TT V TT 50 Ω 50 Ω 50 Ω External On-Board 50 Ω...
Page 217: Differential I/O Standards Termination
Chapter 6: I/O Features in Stratix IV Devices 6–41 Termination Schemes for I/O Standards Differential I/O Standards Termination Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18, HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS. Figure 6–29 through Figure 6–35 show the details of various differential I/O terminations on these devices.
Page 218 6–42 Chapter 6: I/O Features in Stratix IV Devices Termination Schemes for I/O Standards Figure 6–30. Differential HSTL I/O Standard Termination Termination Differential HSTL Class II Differential HSTL Class I V TT V TT V TT V TT V TT V TT 50 Ω...
Page 219: Lvds
LVDS requires a 100- termination resistor between the two signals at the input buffer. Stratix IV devices provide an optional 100- differential termination resistor in the device using on-chip differential termination.
Page 220: Differential Lvpecl
Termination Schemes for I/O Standards Differential LVPECL In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on column and row I/O banks. LVPECL output operation is not supported in Stratix IV devices. LVDS input buffers are used to support LVPECL input operation. AC coupling is required when the LVPECL common-mode voltage of the output buffer is higher than the LVPECL input common-mode voltage.
Page 221: Rsds
Termination Schemes for I/O Standards RSDS Stratix IV devices support the RSDS output standard with data rates up to 230 Mbps using LVDS output buffer types. For transmitters, use two single-ended output buffers with the external one- or three-resistor networks in the column I/O bank, as...
Page 222: Mini-Lvds
Chapter 6: I/O Features in Stratix IV Devices Design Considerations Mini-LVDS Stratix IV devices support the mini-LVDS output standard with data rates up to 340 Mbps using LVDS output buffer types. For transmitters, use two single-ended output buffers with external one- or three-resistor networks, as shown in Figure 6–35.
Page 223: Non-Voltage-Referenced Standards
6–47 Design Considerations Non-Voltage-Referenced Standards Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one , either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any CCIO number of input signals with different I/O standard assignments if it meets the V...
Page 224 6–48 Chapter 6: I/O Features in Stratix IV Devices Design Considerations Document Revision History Table 6–13 lists the revision history for this chapter. Table 6–13. Document Revision History (Part 1 of 2) Date Version Changes Updated the “Programmable Slew Rate Control”...
Page 225 Chapter 6: I/O Features in Stratix IV Devices 6–49 Design Considerations Table 6–13. Document Revision History (Part 2 of 2) Date Version Changes Updated “Modular I/O Banks” on page 6–7. ■ November 2008 Updated Figure 6–3 and Figure 6–21. ■...
Page 226 6–50 Chapter 6: I/O Features in Stratix IV Devices Design Considerations Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 227 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 228 (1) You can bypass each register block. (2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Stratix IV IOE. (3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read and write operations.
Page 229: Memory Interfaces Pin Support
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to indicate that the read data is ready to be captured. This section describes how Stratix IV devices support all these different pins.
Page 230 CQn pin for complementary read-data strobe and clock operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and CQn pins.
Page 231 I/O standards required to support DDR3, DDR2, DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices. The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode ×32/×36.
Page 232 7–6 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 2 of 3) Device Package Side ×4 ×8/×9 ×16/×18 ×32/×36 Refer to: Left/Right...
Page 233 You cannot use these groups if you use the Stratix IV calibrated OCT feature. (3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to “Combining...
Page 234 7–8 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–3. Number of DQS/DQ Groups per Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8C...
Page 235 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–9 Memory Interfaces Pin Support Figure 7–4. Number of DQS/DQ Groups per Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7A I/O Bank 8A...
Page 236 7–10 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–5. Number of DQS/DQ Groups per Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package I/O Bank 7C I/O Bank 8A I/O Bank 8C...
Page 237 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–11 Memory Interfaces Pin Support Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine BGA Package I/O Bank 7A I/O Bank 8A...
Page 238 7–12 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the 1152-Pin FineLine BGA Package I/O Bank 7A (3)
Page 239 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–13 Memory Interfaces Pin Support Figure 7–8. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B I/O Bank 8A...
Page 240 7–14 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–9. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 241 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–15 Memory Interfaces Pin Support Figure 7–10. Number of DQS/DQ Groups per Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 242 7–16 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–11. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1517-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B I/O Bank 8A...
Page 243 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–17 Memory Interfaces Pin Support Figure 7–12. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 244 7–18 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–13. Number of DQS/DQ Groups per Bank in EP4SE530 and EP4SE820 Devices in the 1517-pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 245 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–19 Memory Interfaces Pin Support Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B...
Page 246 7–20 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–15. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine BGA Package I/O Bank 7C I/O Bank 7B...
Page 247 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–21 Memory Interfaces Pin Support Figure 7–16. Number of DQS/DQ Groups per Bank in EP4SE530 Devices in the 1760-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 248 7–22 Chapter 7: External Memory Interfaces in Stratix IV Devices Memory Interfaces Pin Support Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package I/O Bank 8A I/O Bank 8B I/O Bank 8C...
Page 249 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–23 Memory Interfaces Pin Support Figure 7–18. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package I/O Bank 8A I/O Bank 8B...
Page 250 Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose up to four ×4 DQS/DQ groups, depending on your configuration scheme. The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY, respectively, where X indicates the DQS/DQ grouping number and Y indicates whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.
Page 251 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–25 Memory Interfaces Pin Support The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin table. The numbering scheme starts from the top-left corner of the device going counter-clockwise in a die-top view.
Page 252: Combining ×16/×18 Dqs/Dq Groups For A ×36 Qdr Ii+/Qdr Ii Sram Interface
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in the FPGA. This is the only connection on the board that you need to change for this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV devices also apply for this implementation.
Page 253: Rules To Combine Groups
Table 7–3 lists the possible combinations to use two ×16/×18 DQS/DQ groups to form a ×32/×36 group on Stratix IV devices lacking a native ×32/×36 DQS/DQ group. Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 1 of 2)
Page 254 (3) Although it is possible to combine the ×16/×18 DQS/DQ groups from I/O banks 1A and 1C, 2A and 2C, 5A and 5C, and 6A and 6C, Altera does not recommend this due to the size of the package. Similarly, crossing a bank number (for example, combining groups from I/O banks 6C and 5C) is not supported in this package.
Page 255: Stratix Iv External Memory Interface Features
The ALTMEMPHY megafunction allows you to use these external memory interface features and helps set up the physical interface (PHY) best suited for your system. This section describes each Stratix IV device feature that is used in external memory interfaces from the DQS phase-shift circuitry, DQS logic block, leveling multiplexers, and dynamic OCT control block.
Page 256 7–30 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Figure 7–21 shows how the DQS phase-shift circuitry is connected to the DQS/CQ and CQn pins in the device where memory interfaces are supported on all sides of the Stratix IV device.
Page 257 There are a maximum of four DLLs in a Stratix IV device, located in each corner of the device. These four DLLs support a maximum of four unique frequencies, with each DLL running at one frequency.
Page 258 Stratix IV External Memory Interface Features Figure 7–22 shows the DLL and I/O bank locations in Stratix IV devices from a die-top view if all sides of the device support external memory interfaces. Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
Page 259 Table 7–5 through Table 7–17 lists the available DLL reference clock input resources for the Stratix IV device family. When you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to No Compensation to achieve better performance or the Quartus II software changes it automatically.
Page 260 7–34 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–6. DLL Reference Clock Input for EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right) (Corner)
Page 261 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–35 Stratix IV External Memory Interface Features Table 7–8. DLL Reference Clock Input for EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package (with 24 Transceivers) CLKIN CLKIN (Top/Bottom) (Left/Right)
Page 262 7–36 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–10. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right)
Page 263 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–37 Stratix IV External Memory Interface Features Table 7–12. DLL Reference Clock Input for EP4SE530 and EP4SE820 Devices in the 1517- and 1760-Pin FineLine BGA Packages CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom)
Page 264 7–38 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–14. DLL Reference Clock Input for EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom)
Page 265 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–39 Stratix IV External Memory Interface Features Table 7–16. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine BGA Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right)
Page 266 7–40 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Figure 7–23 shows a simple block diagram of the DLL. The input reference clock goes into the DLL to a chain of up to 16 delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock.
Page 267: Phase Offset Control
Chapter 7: External Memory Interfaces in Stratix IV Devices 7–41 Stratix IV External Memory Interface Features There are eight different frequency modes for the Stratix IV DLL, as listed in Table 7–18. Each frequency mode provides different phase shift selections. In frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to implement the phase-shift delay.
Page 268 7–42 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features You can use either a static phase offset or a dynamic phase offset to implement the additional phase shift. The available additional phase shift is implemented in 2’s: complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and...
Page 269: Dqs Logic Block
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7–5 on page 7–33 through Table 7–17 on page 7–39. (2) The dqsenable signal can also come from the Stratix IV FPGA fabric.
Page 270: Dqs Delay Chain
7–44 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features DQS Delay Chain DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ and CQn signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.
Page 271: Dqs Postamble Circuitry
DQS is in a postamble state do not affect the DQ IOE registers. In addition to the dedicated postamble register, Stratix IV devices also have an HDR block inside the postamble enable circuitry. Use these registers if the controller is running at half the frequency of the I/Os.
Page 272: Leveling Circuitry
FPGA from the memory is also staggered in a similar way. Stratix IV FPGAs have leveling circuitry to address these two situations. There is one leveling circuitry per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each has one leveling circuitry).
Page 273 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–47 Stratix IV External Memory Interface Features Figure 7–28 Figure 7–29 show the Stratix IV write- and read-leveling circuitry. Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers Write clk Write-Leveled DQS Clock...
Page 274: Dynamic On-Chip Termination Control
7–48 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and write-leveling during the initialization process. For more information about the ALTMEMPHY megafunction, refer to the...
Page 275: I/O Element Registers
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout. (9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn signals are automatically inverted.
Page 276 Circuitry” on page 7–46. Figure 7–32 shows the registers available in the Stratix IV output and output-enable paths. The path is divided into the HDR block, resynchronization registers, and output and output-enable registers. The device can bypass each block of the output and output-enable path.
Page 277 Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers Half Data Rate to Single Data Rate Output-Enable Registers Alignment Registers (4) From Core (2) Double Data Rate Output-Enable Registers From Core (2) OE Reg A Half Data Rate to Single Data Rate Output Registers...
Page 278: Delay Chain
Delay Chain Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the DQS logic blocks. You can control the delay chain setting through the I/O or the DQS configuration block output.
Page 279 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–53 Stratix IV External Memory Interface Features Figure 7–34 shows the delay chains in an I/O block. Figure 7–34. Delay Chains in an I/O Block rtena D5 OCT D5 Output- (outputdelaysetting1 +...
Page 280: I/O Configuration Block And Dqs Configuration Block
7–54 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features I/O Configuration Block and DQS Configuration Block The I/O configuration block and the DQS configuration block are shift registers that you can use to dynamically change the settings of various device configuration bits.
Page 281 Chapter 7: External Memory Interfaces in Stratix IV Devices 7–55 Stratix IV External Memory Interface Features Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2) Bit Name 34..36 octdelaysetting2[0..2] enadataoutbypass enadqsenablephasetransferreg enaoctphasetransferreg enaoutputphasetransferreg enainputphasetransferreg resyncinputphaseinvert dqsenablectrlphaseinvert dqoutputphaseinvert dqsoutputphaseinvert Document Revision History Table 7–21...
Page 282 7–56 Chapter 7: External Memory Interfaces in Stratix IV Devices Stratix IV External Memory Interface Features Table 7–21. Document Revision History (Part 2 of 2) Date Version Changes Updated the “Memory Interfaces Pin Support” and “Combining ×16/×18 DQS/DQ Groups ■...
Page 283: Overview
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 284 ■ Reduced swing differential signaling (RSDS) ■ In the Stratix IV device family, I/Os are divided into row and column I/Os. Figure 8–1 shows I/O bank support for the Stratix IV device family. The row I/Os provide dedicated SERDES circuitry.
Page 285: Locations Of The I/O Banks
LVDS interface has the Use External PLL option enabled. Locations of the I/O Banks Stratix IV I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that supports high-speed differential I/Os is located in banks in the right and left side of the device.
Page 286: Lvds Channels
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS Channels Figure 8–3 shows a high-level chip overview of the Stratix IV GT and GX devices. Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices General Purpose General Purpose I/O and Memory...
Page 287 LVDS I/Os supported in Stratix IV E devices. You can design the LVDS I/Os as true LVDS buffers or emulated LVDS buffers, as long as the combination of the two do not exceed the maximum count.
Page 288 Table 8–3 Table 8–4 list the maximum number of row and column LVDS I/Os supported in Stratix IV GT devices. Table 8–3. LVDS Channels Supported in Stratix IV GT Device Row I/O Banks Device 1517-pin FineLine BGA 1932-pin FineLine BGA...
Page 289 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–7 LVDS Channels Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks (Part 2 of 2) 1152-Pin 780-Pin 1152-Pin 1517-Pin 1760-Pin 1932-Pin Device FineLine BGA...
Page 290: Lvds Serdes
8–8 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS SERDES LVDS SERDES Figure 8–4 shows a transmitter and receiver block diagram for the LVDS SERDES circuitry in the left and right banks. This diagram shows the interface signals of the transmitter and receiver data path.
Page 291: Altlvds Port List
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–9 ALTLVDS Port List ALTLVDS Port List Table 8–7 lists the interface signals for an LVDS transmitter and receiver. Table 8–7. Port List of the LVDS Interface (ALTLVDS)
Page 292 8–10 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices ALTLVDS Port List Table 8–7. Port List of the LVDS Interface (ALTLVDS) (Part 2 of 3) Input / Port Name Description Output LVDS Receiver Interface Signals Input LVDS receiver serial data input port.
Page 293: Differential Transmitter
Guide. Differential Transmitter The Stratix IV transmitter has a dedicated circuitry to provide support for LVDS signaling. The dedicated circuitry consists of a differential buffer, a serializer, and left and right PLLs that can be shared between the transmitter and receiver. The differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels.
Page 294 8–12 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at serial data rate) generated from PLL_Lx (left PLL) or PLL_Rx (right PLL) clocks the load and shift registers.
Page 295 Left/Right LVDS_LOAD_EN You can bypass the Stratix IV serializer to support DDR (×2) and SDR (×1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode.
Page 296 8–14 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter Programmable V and Programmable Pre-Emphasis Stratix IV LVDS transmitters support programmable pre-emphasis and programmable V . Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line.
Page 297: Programmable Vod
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–15 Differential Transmitter Pre-emphasis is an important feature for high-speed transmission. Without pre-emphasis, the output current is limited by the V setting and the output impedance of the driver. At high frequency, the slew rate may not be fast enough to reach full V before the next edge, producing pattern-dependent jitter.
Page 298: Programmable Pre-Emphasis
8–16 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Transmitter Programmable Pre-Emphasis Four different settings are allowed for pre-emphasis from the Assignment Editor for each LVDS output channel. Table 8–9 lists the assignment name and its possible values for programmable pre-emphasis in the Quartus II software Assignment Editor.
Page 299: Differential Receiver
Figure 8–12 shows the hardware blocks of the Stratix IV receiver. The receiver has a differential buffer and left and right PLLs that can be shared between the transmitter and receiver, a DPA block, a synchronizer, a data realignment block, and a deserializer. The differential buffer can receive LVDS, mini-LVDS, and RSDS signal levels, which are statically set in the Quartus II software Assignment Editor.
Page 300: Differential I/O Termination
8–18 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock and the received serial data to compensate skew. In DPA mode, the DPA circuitry automatically chooses the best phase to compensate for the skew between the source synchronous clock and the received serial data.
Page 301: Receiver Hardware Blocks
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–19 Differential Receiver Figure 8–13 shows device on-chip termination. Figure 8–13. On-Chip Differential I/O Termination Stratix IV Differential LVDS Receiver with On-Chip 100 Ω Termination Transmitter = 50 Ω...
Page 302: Synchronizer
8–20 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver The DPA block continuously monitors the phase of the incoming serial data and selects a new clock phase if needed. You can prevent the DPA from selecting a new clock phase by asserting the optional RX_DPLL_HOLD port, which is available for each channel.
Page 303 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–21 Differential Receiver ■ Valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN. Figure 8–15 shows receiver output (RX_OUT) after one bit slip pulse with the deserialization factor set to 4.
Page 304: Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,...
Page 305 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–23 Differential Receiver When using non-DPA receivers, you must drive the PLL from a dedicated and compensated clock input pin. Compensated clock inputs are dedicated clock pins in the same I/O bank as the PLL.
Page 306: Dpa Mode
8–24 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Receiver DPA Mode Figure 8–19 shows the DPA mode datapath, where all the hardware blocks mentioned “Receiver Hardware Blocks” on page 8–19 are active. The DPA block chooses the best possible clock (DPA_diffioclk) from the eight fast clocks sent by the left and right PLL.
Page 307: Soft-Cdr Mode
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–25 Differential Receiver Soft-CDR Mode The Stratix IV LVDS channel offers soft-CDR mode to support the Gigabit Ethernet and SGMII protocols. A receiver PLL uses the local clock source for reference. Figure 8–20 shows the soft-CDR mode datapath.
Page 308: Lvds Interface With The Use External Pll Option Enabled
You can use every LVDS channel in soft-CDR mode and can drive the FPGA fabric using the periphery clock network in the Stratix IV device family. The rx_dpa_locked signal is not valid in soft-CDR mode because the DPA continuously changes its phase to track PPM differences between the upstream transmitter and the local receiver input reference clocks.
Page 309 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–27 LVDS Interface with the Use External PLL Option Enabled Table 8–10. Signal Interface Between ALTPLL and ALTLVDS_TX and ALTLVDS_RX Megafunctions (Part 2 of 2) From the ALTPLL...
Page 310 8–28 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices LVDS Interface with the Use External PLL Option Enabled Example 8–1 shows how to generate three output clocks using an ALTPLL megafunction. Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction LVDS data rate = 1 Gbps;...
Page 311: Left And Right Plls (Pll_Lx And Pll_Rx)
Left and Right PLLs (PLL_Lx and PLL_Rx) The Stratix IV device family contains up to eight left and right PLLs with up to four PLLs located on the left side and four on the right side of the device. The left PLLs can support high-speed differential I/O banks on the left side;...
Page 312: Stratix Iv Clocking
PLL clocking in the Stratix IV device family. For more information about PLL clocking restrictions, refer to “Differential Pin Placement Guidelines” on page 8–38. Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs Corner Corner PLL_R1 PLL_L1...
Page 313: Source-Synchronous Timing Budget
This section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for the Stratix IV device family, and how to use these timing parameters to determine a design’s maximum performance.
Page 314 8–32 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget For other serialization factors, use the Quartus II software tools to find the bit position within the word. Table 8–11 lists the bit positions after deserialization.
Page 315: Transmitter Channel-To-Channel Skew
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–33 Source-Synchronous Timing Budget Transmitter Channel-to-Channel Skew Transmitter channel-to-channel skew (TCCS) is an important parameter based on the Stratix IV transmitter in a source synchronous differential interface. This parameter is used in receiver skew margin calculation.
Page 316 8–34 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget Figure 8–27 shows the relationship between the RSKM, TCCS, and the receiver’s SW. You must calculate the RSKM value to decide whether or not data can be sampled properly by the LVDS receiver with the given data rate and device.
Page 317 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–35 Source-Synchronous Timing Budget For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing Analyzer.
Page 318 8–36 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Source-Synchronous Timing Budget Figure 8–29 shows the setting parameters for the Set Input Delay option. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
Page 319 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–37 Source-Synchronous Timing Budget 4. Select the LVDS receiver serial input ports (from the list) according to the input delay you set. Click OK. 5. In the Set Input Delay window, set the appropriate values in the Input Delay Options section and Delay value.
Page 320: Differential Pin Placement Guidelines
Guidelines for DPA-Enabled Differential Channels The Stratix IV device family has differential receivers and transmitters in I/O banks on the left and right sides of the device. Each receiver has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
Page 321 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–39 Differential Pin Placement Guidelines You do not need a separation if a single left and right PLL is driving the DPA-enabled channels as well as DPA-disabled channels.
Page 322: Using Both Center Left And Right Plls
8–40 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Using Both Center Left and Right PLLs You can use both center left and right PLLs to drive DPA-enabled channels simultaneously, as long as they drive these channels in their adjacent banks only, as...
Page 323 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–41 Differential Pin Placement Guidelines Figure 8–33. Invalid Placement of DPA-Enabled Differential I/Os Driven by Both Center Left and Right PLLs DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled...
Page 324: Guidelines For Dpa-Disabled Differential Channels
Differential Pin Placement Guidelines Guidelines for DPA-Disabled Differential Channels When you use DPA-disabled channels in the left and right banks of a Stratix IV device, you must adhere to the guidelines in the following sections. When using non-DPA receivers, you must drive the PLL from a dedicated and compensated clock input pin.
Page 325 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–43 Differential Pin Placement Guidelines Figure 8–34. Corner and Center Left and Right PLLs Driving DPA-Disabled Differential I/Os in the Same Bank Corner Left/Right Corner Left/ Right Reference...
Page 326 8–44 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Figure 8–35. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven by the Corner and Center Left and Right PLLs...
Page 327: Using Both Center Left And Right Plls
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–45 Differential Pin Placement Guidelines Using Both Center Left and Right PLLs You can use both center left and right PLLs simultaneously to drive DPA-disabled channels on upper and lower differential banks. Unlike DPA-enabled channels, the center left and right PLLs can drive cross-banks.
Page 328 8–46 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Document Revision History Table 8–12 lists the revision history for this chapter. Table 8–12. Document Revision History (Part 1 of 2) Date Version...
Page 329 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices 8–47 Differential Pin Placement Guidelines Table 8–12. Document Revision History (Part 2 of 2) Date Version Changes Updated Figure 8–2, Figure 8–3, Figure 8–21, Figure 8–34. ■ Removed Figure 8–31.
Page 330 8–48 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices Differential Pin Placement Guidelines Stratix IV Device Handbook September 2012 Altera Corporation Volume 1...
Page 331 Section III. System Integration This section includes the following chapters: Chapter 9, Hot Socketing and Power-On Reset in Stratix IV Devices ■ ■ Chapter 10, Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices ■ Chapter 11, SEU Mitigation in Stratix IV Devices ■...
Page 332 III–2 Section III: System Integration Stratix IV Device Handbook January 2016 Altera Corporation Volume 1...
Page 333: Stratix Iv Hot-Socketing Specifications
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 334: Stratix Iv Devices Can Be Driven Before Power Up
In a hot-socketing situation, the Stratix IV device’s output buffers are turned off during system power up or power down. Also, the Stratix IV device does not drive out until the device is configured and working within the recommended operating conditions.
Page 335: Hot-Socketing Feature Implementation In Stratix Iv Devices
) and keeps the I/O pins tri-stated until the device is in user mode. CCPGM CCPD The weak pull-up resistor (R) in the Stratix IV input/output element (IOE) keeps the I/O pins from floating. The 3.0-V tolerance control circuit permits the I/O pins to be driven by 3.0 V before the V...
Page 336: Power-On Reset Circuitry
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices Power-On Reset Circuitry Power-On Reset Circuitry When power is applied to a Stratix IV device, a POR event occurs if the power supply reaches the recommended operating range within the maximum power supply ramp time (t ).
Page 337: Power-On Reset Specifications
CCBAT no affect on the device configuration. The POR specification is designed to ensure that all the circuits in the Stratix IV device are at certain known states during power up. The POR signal pulse width is programmable using the PORSEL input pin. When the PORSEL pin is connected to GND, the POR delay time is 100 to 300 ms.
Page 338 ■ Updated the introduction and the “Stratix IV Hot-Socketing Specifications”, “Insertion or ■ Removal of a Stratix IV Device from a Powered-Up System”, “Hot-Socketing Feature Implementation in Stratix IV Devices”, “Power-On Reset Circuitry”, and “Power-On Reset Specifications” sections. March 2010 Updated Table 9–1 and Table 9–2.
Page 339: Overview
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 340: Configuration Devices
® Altera serial configuration devices support a single-device and multi-device configuration solution for Stratix IV devices and are used in the fast AS configuration scheme. Serial configuration devices offer a low-cost, low pin-count configuration solution. For information about serial configuration devices, refer to the...
Page 341 Table 10–1: (1) Stratix IV devices only support fast AS configuration. You must use either EPCS64 or EPCS128 devices to configure a Stratix IV device in fast AS mode. (2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
Page 342: Configuration Features
If your system already contains a common flash interface (CFI) flash memory, you can use it for Stratix IV device configuration storage as well. The MAX II parallel flash loader (PFL) feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and provides the logic to control configuration from the flash memory device to the Stratix IV device.
Page 343: Power-On Reset Circuit
CCPD below the threshold voltage. In Stratix IV devices, a pin-selectable option (PORSEL) is provided that allows you to select between the standard POR time or fast POR time. When PORSEL is driven low, the standard POR time is 100 ms < T <...
Page 344: Fast Passive Parallel Configuration
DCLK Note to Figure 10–1: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V must be CCPGM high enough to meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 345 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–7 Fast Passive Parallel Configuration After power-up, the Stratix IV device goes through a POR. The POR delay depends on the PORSEL pin setting. When PORSEL is driven low, the standard POR time is 100 ms < T <...
Page 346 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Fast Passive Parallel Configuration In Stratix IV devices, the initialization clock source is either the internal oscillator or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization.
Page 347 Stratix IV device when you use the decompression and/or design security features. two clock cycles after the last data byte was latched into the Stratix IV device when ■...
Page 348 DCLK Note to Figure 10–2: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough CCPGM to meet the V specification of the I/O standard on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 349 DCLK Notes to Figure 10–3: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM.
Page 350: Fpp Configuration Timing
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins depends on the dual-purpose pin settings.
Page 351 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–13 Fast Passive Parallel Configuration Table 10–4. FPP Timing Parameters for Stratix IV Devices (Part 2 of 2) (Note Minimum Maximum Symbol Parameter Units Stratix IV Stratix IV...
Page 352 (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins depends on the dual-purpose pin settings.
Page 353 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–15 Fast Passive Parallel Configuration Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features Enabled (Note (Part 2 of 2)
Page 354: Fpp Configuration Using A Microprocessor
Fast Active Serial Configuration (Serial Configuration Devices) In the fast AS configuration scheme, Stratix IV devices are configured using a serial configuration device. These configuration devices are low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor.
Page 355: Vccpgm Pins
3.3 V power supply to power the EPCS device. The EPCS device and the VCCPGM pins on the Stratix IV device may share the same 3.0 V power supply. After power-up, the Stratix IV devices go through a POR. The POR delay depends on the PORSEL pin setting.
Page 356 (DATA) pin, which connects to the DATA0 input of the Stratix IV devices. After all the configuration bits are received by the Stratix IV device, it releases the open-drain CONF_DONE pin, which is pulled high by an external 10-k resistor.
Page 357 STATUS When the Stratix IV device is in user mode, you can initiate reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin must be low for at least 2 s. When nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Page 358 10–7: (1) Connect the pull-up resistors to V at a 3.0-V supply. CCPGM (2) Connect the repeater buffers between the Stratix IV master and slave device(s) for . This is to prevent potential signal DATA[0] DCLK integrity and clock skew problems.
Page 359 The same copy of the .sof configures the master Stratix IV device and all remaining slave devices concurrently. All Stratix IV devices must be the same density and package. To configure four identical Stratix IV devices with the same .sof, set up the chain as shown in Figure 10–8.
Page 360: Estimating Active Serial Configuration Time
(1) Connect the pull-up resistors to V at a 3.0-V supply. CCPGM (2) Connect the repeater buffers between the Stratix IV master and slave device(s) for DATA[0] and DCLK. This is to prevent potential signal integrity and clock skew problems. Estimating Active Serial Configuration Time Active serial configuration time is dominated by the time it takes to transfer data from the serial configuration device to the Stratix IV device.
Page 361: Programming Serial Configuration Devices
During in-system programming, the download cable disables device access to the AS interface by driving the nCE pin high. Stratix IV devices are also held in reset by a low level on nCONFIG. After programming is complete, the download cable releases nCE...
Page 362 10–24 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Fast Active Serial Configuration (Serial Configuration Devices) For more information about the USB-Blaster download cable, refer to the USB-Blaster Download Cable User Guide. For more information about the ByteBlaster II cable, refer...
Page 363: Guidelines For Connecting Serial Configuration Devices On An As Interface
ASDO Passive Serial Configuration You can program a PS configuration for Stratix IV devices using an intelligent host, such as a MAX II device or microprocessor with flash memory, or a download cable. In the PS scheme, an external host (a MAX II device, embedded processor, or host PC) controls configuration.
Page 364: Ps Configuration Using A Max Ii Device As An External Host
MSEL0 Note to Figure 10–10: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V must be CCPGM high enough to meet the V specification of the I/O on the device and the external host. Altera recommends powering...
Page 365 Whenever the nCONFIG line is released high, ensure that the first DCLK and DATA are not driven unintentionally. The Stratix IV device receives configuration data on the DATA0 pin and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Page 366 Quartus II software from the General tab of the Device and Pin Options dialog box) is turned on, the Stratix IV device releases nSTATUS after a reset time-out period (a maximum of 500 s). After nSTATUS is released and pulled high by a pull-up resistor, the MAX II device can try to reconfigure the target device without needing to pulse nCONFIG low.
Page 367 DCLK Note to Figure 10–11: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM (2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
Page 368 DCLK Notes to Figure 10–12: (1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V must be high enough to CCPGM meet the V specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V CCPGM (2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
Page 369: Ps Configuration Timing
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay. (3) After power-up, before and during configuration, CONF_DONE is low.
Page 370: Ps Configuration Using A Microprocessor
USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable. After power-up, Stratix IV devices go through a POR. The POR delay depends on the PORSEL pin setting. When PORSEL is driven low, the standard POR time is 100 ms <...
Page 371 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–33 Passive Serial Configuration The configuration cycle consists of three stages—reset, configuration, and initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration in this scheme, the download cable generates a low-to-high transition on the nCONFIG pin.
Page 372 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Passive Serial Configuration You can use a download cable to configure multiple Stratix IV devices by connecting each device’s nCEO pin to the subsequent device’s nCE pin. The first device’s nCE pin is connected to GND, while its nCEO pin is connected to the nCE of the next device in the chain.
Page 373: Jtag Configuration
Stratix IV devices during PS configuration, PS configuration is terminated and JTAG configuration begins. You cannot use the Stratix IV decompression or design security features if you are configuring your Stratix IV device when using JTAG-based configuration. A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST.
Page 374 10–36 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices JTAG Configuration During JTAG configuration, you can download data to the device on the PCB through the USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable. Configuring devices through a cable is similar to programming devices in-system, except you must connect the TRST pin to V .
Page 375 Signal Description On all Stratix IV devices in the chain, nCE must be driven low by connecting it to GND, pulling it low using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or PS configuration chains, the nCE pins must be connected to GND during JTAG configuration or JTAG must be configured in the same order as the configuration chain.
Page 376 10–38 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices JTAG Configuration Table 10–8. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2) Signal Description Driven high by connecting to V , pulling up using a resistor, or driven high by...
Page 377 JTAG configured. You can place other Altera devices that have JTAG support in the same JTAG chain for device programming and configuration.
Page 378: Jam Stapl
Notes to Figure 10–18: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. must be high enough to meet the V specification of the I/O on the device.
Page 379 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–41 Device Configuration Pins Table 10–9. Stratix IV Configuration Pin Summary (Part 2 of 2) (Note 1) Description Input/Output Dedicated Powered By Configuration Mode Input — All modes except JTAG...
Page 380 You must connect these pins properly on your board for successful configuration. Some of these pins may not be required for your configuration schemes. Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 1 of 4) Configuration Pin Name...
Page 381 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–43 Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 2 of 4) Configuration Pin Name User Mode Pin Type Description Scheme Three-bit configuration input that sets the Stratix IV device configuration scheme.
Page 382 10–44 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 3 of 4) Configuration Pin Name User Mode Pin Type Description Scheme...
Page 383 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–45 Device Configuration Pins Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 4 of 4) Configuration Pin Name User Mode Pin Type Description Scheme...
Page 384 10–46 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Device Configuration Pins Table 10–11 lists the optional configuration pins. If these optional configuration pins are not enabled in the Quartus II software, they are available as general-purpose user I/O pins.
Page 385 (typically 25 k  ). If you plan to use the SignalTap ® embedded logic array analyzer, you must connect the JTAG pins of the Stratix IV device to a JTAG header on your board. Table 10–12. Dedicated JTAG Pins...
Page 386: Configuration Data Decompression
Preliminary data indicates that compression typically reduces the configuration bitstream size by 30% to 55% based on the designs used. Stratix IV devices support decompression in the FPP (when using a MAX II device or microprocessor + flash), fast AS, and PS configuration schemes. The Stratix IV decompression feature is not available in the JTAG configuration scheme.
Page 387 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–49 Configuration Data Decompression 3. In the Configuration settings tab, turn on Generate compressed bitstreams (as shown in Figure 10–19). Figure 10–19. Enabling Compression for Stratix IV Bitstreams in Compiler Settings You can also enable compression when creating programming files from the Convert Programming Files window.
Page 388: Remote System Upgrades
In a multi-device FPP configuration chain (with a MAX II device or microprocessor + flash), all Stratix IV devices in the chain must either enable or disable the decompression feature. You cannot selectively enable the compression feature for each device in the chain because of the DATA and DCLK relationship.
Page 389: Functional Description
Stratix IV devices have remote system upgrade processes that involve the following steps: 1. A Nios II processor (or user logic) implemented in the Stratix IV device logic array receives new configuration data from a remote location. The connection to the...
Page 390 10–52 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Remote System Upgrades Figure 10–21 shows the steps required for performing remote configuration updates. (The numbers in Figure 10–21 coincide with the steps just mentioned.) Figure 10–21. Functional Diagram of Stratix IV Remote System Upgrade...
Page 391: Enabling Remote Update
10–62. Enabling Remote Update You can enable remote update for Stratix IV devices in the Quartus II software before design compilation (in the Compiler Settings menu). In remote update mode, the auto-restart configuration after error option is always enabled. To enable remote update in the project’s compiler settings, in the Quartus II software, follow these...
Page 392: Configuration Image Types
Additionally, remote update mode features a user watchdog timer that determines the validity of an application configuration. When a Stratix IV device is first powered up in remote update mode, it loads the factory configuration located at page zero (page registers PGM[23:0] = 24'b0). Always store the factory configuration image for your system at page address zero.
Page 393 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–55 Remote System Upgrade Mode The factory image is user-designed and contains soft logic to: ■ Process any errors based on status information from the dedicated remote system...
Page 394 10–56 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Remote System Upgrade Mode The user watchdog timer is automatically disabled for factory configurations. For more information about the user watchdog timer, refer to “User Watchdog Timer” on page 10–61.
Page 395: Dedicated Remote System Upgrade Circuitry
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–57 Dedicated Remote System Upgrade Circuitry Dedicated Remote System Upgrade Circuitry This section describes the implementation of the Stratix IV remote system upgrade dedicated circuitry. The remote system upgrade circuitry is implemented in hard logic.
Page 396: Remote System Upgrade Registers
10–58 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Dedicated Remote System Upgrade Circuitry Remote System Upgrade Registers The remote system upgrade block contains a series of registers that store the page addresses, watchdog timer settings, and status information.
Page 397: Remote System Upgrade Status Register
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–59 Dedicated Remote System Upgrade Circuitry The application-not-factory (AnF) bit indicates whether the current configuration loaded in the Stratix IV device is the factory configuration or an application configuration.
Page 398: Remote System Upgrade State Machine
Table 10–16: (1) Logic array reconfiguration forces the system to load the application configuration data into the Stratix IV device. This occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. Remote System Upgrade State Machine...
Page 399 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–61 Dedicated Remote System Upgrade Circuitry The remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded.
Page 400: User Watchdog Timer
10–62 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Dedicated Remote System Upgrade Circuitry User Watchdog Timer The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. The system uses the timer to detect functional errors after an application configuration is successfully loaded into the Stratix IV device.
Page 401: Quartus Ii Software Support
The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Stratix IV device logic. This implementation is suitable for designs that implement the factory configuration functions using a Nios II processor or user logic in the device.
Page 402: Design Security
Stratix IV devices using the advanced encryption standard (AES). It also covers the new security modes available in Stratix IV devices. As Stratix IV devices continue play a role in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering.
Page 403: Stratix Iv Security Protection
Security Against Copying The security key is securely stored in the Stratix IV device and cannot be read out through any interfaces. In addition, as configuration file read-back is not supported in Stratix IV devices, the design information cannot be copied.
Page 404: Stratix Iv Design Security Solution
10–19: (1) Key programming is carried out using the JTAG interface. You can program the non-volatile key to the Stratix IV device without an external battery. Also, there are no additional requirements to any of the Stratix IV power supply inputs.
Page 405: Security Modes Available
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–67 Design Security At system power-up, the external memory device sends the encrypted configuration file to the Stratix IV device. Figure 10–29. Design Security (Note 1) Stratix IV Device...
Page 406: No Key Operation
10–68 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Design Security Enabling the tamper protection bit disables test mode in Stratix IV devices. This process is irreversible and prevents Altera from conducting carry-out failure analysis if test mode is disabled.
Page 407 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices 10–69 Design Security Table 10–21 lists the configuration modes allowed in each of the security modes. Table 10–21. Allowed Configuration Modes for Various Security Modes (Note 1)
Page 408 10–70 Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Design Security Table 10–22. Document Revision History (Part 2 of 2) Date Version Changes Updated the “FPP Configuration Using a MAX II Device as an External Host”, “Fast Active ■...
Page 409 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 410: Error Detection Fundamentals
If the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. The error detection CRC feature uses the same concept. When Stratix IV devices are configured successfully and are in user mode, the error detection CRC feature ensures the integrity of the configuration data.
Page 411 This causes the CRC engine to start searching for the error bit location. Error detection in Stratix IV devices calculates CRC check bits for each frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a frame, it can detect all single-bit, double-bit, and three-bit errors.
Page 412 A JTAG instruction, EDERROR_INJECT, is provided to test the capability of the error detection block. This instruction is able to change the content of the 21-bit JTAG fault injection register that is used for error injection in Stratix IV devices, enabling the testing of the error detection block.
Page 413: Automated Single-Event Upset Detection
SEU. You can implement the error detection CRC feature with existing circuitry in Stratix IV devices, eliminating the need for external logic. The CRC_ERROR pin reports a soft error when the configuration CRAM data is corrupted. You must decide whether to reconfigure the device or to ignore the error.
Page 414: Error Detection Block
Chapter 11: SEU Mitigation in Stratix IV Devices Error Detection Block Error Detection Block You can enable the Stratix IV device error detection block in the Quartus II software (refer to “Software Support” on page 11–10). This block contains the logic necessary to calculate the 16-bit CRC signature for the configuration CRAM bits in the device.
Page 415: Error Detection Registers
Chapter 11: SEU Mitigation in Stratix IV Devices 11–7 Error Detection Block Error Detection Registers There is one set of 16-bit registers in the error detection circuitry that stores the computed CRC signature. A non-zero value on the syndrome register causes the CRC_ERROR pin to be set high.
Page 416: Error Detection Timing
11–8 Chapter 11: SEU Mitigation in Stratix IV Devices Error Detection Timing Table 11–4. Error Detection Registers (Part 2 of 2) Register Description This register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. It includes a clock enable that must be asserted prior JTAG Update Register to being sampled into the JTAG shift register.
Page 417 The error detection frequency reflects the frequency of the error detection process for a frame because the CRC calculation in the Stratix IV device is done on a per-frame basis. You must monitor the error message to avoid missing information in the error message register.
Page 418: Software Support
Quartus II software. To enable the error detection feature using CRC, follow these steps: 1. Open the Quartus II software and load a project using a Stratix IV device. 2. On the Assignments menu, click Settings. The Settings dialog box is shown.
Page 419: Recovering From Crc Errors
8. Click OK. Recovering From CRC Errors The system that the Stratix IV device resides in must control device reconfiguration. After detecting an error on the CRC_ERROR pin, strobing the nCONFIG signal low directs the system to perform the reconfiguration at a time when it is safe for the system to reconfigure the device.
Page 420 11–12 Chapter 11: SEU Mitigation in Stratix IV Devices Recovering From CRC Errors Document Revision History Table 11–8 lists the revision history for this chapter. Table 11–8. Document Revision History Date Version Changes Applied new template. ■ February 2011 Minor Text edits.
Page 421: Bst Architecture
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 422: Bst Operation Control
(1) For the F1932 package of EP4SGX290 and EP4SGX360 devices, the boundary-scan register length is 2970. Table 12–2 lists the IDCODE information for Stratix IV devices. Table 12–2. IDCODE Information for Stratix IV Devices (Part 1 of 2) IDCODE (32 Bits) Device...
Page 423 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices 12–3 BST Operation Control Table 12–2. IDCODE Information for Stratix IV Devices (Part 2 of 2) IDCODE (32 Bits) Device Manufacturer Identity Version (4 Bits) Part Number (16 Bits) (11 Bits)
Page 424: I/O Voltage Support In A Jtag Chain
BST Circuitry The IEEE Std. 1149.1 BST circuitry is enabled after device power-up. You can perform BST on Stratix IV devices before, during, and after configuration. Stratix IV devices support BYPASS, IDCODE, and SAMPLE JTAG instructions during configuration without interrupting configuration. To send all other JTAG instructions, you must interrupt configuration using the CONFIG_IO JTAG instruction.
Page 425 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices 12–5 BSDL Support Document Revision History Table 12–3 lists the revision history for this chapter. Table 12–3. Document Revision History Date Version Changes Applied new template. ■ February 2011 Minor text edits.
Page 426 12–6 Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices BSDL Support Stratix IV Device Handbook February 2011 Altera Corporation Volume 1...
Page 427: Overview
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 428: Stratix Iv Power Technology
The following sections describe Stratix IV programmable power technology. Programmable Power Technology Stratix IV devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation performed by the Quartus II software without user intervention. Setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies brought into the Stratix IV device.
Page 429: Stratix Iv External Power Supply Requirements
Stratix IV External Power Supply Requirements This section describes the different external power supplies required to power Stratix IV devices. You can supply some of the power supply pins with the same external power supply, provided they have the same voltage level.
Page 430: Temperature Sensing Diode
Temperature Sensing Diode Temperature Sensing Diode The Stratix IV TSD uses the characteristics of a PN junction diode to determine die temperature. Knowing the junction temperature is crucial for thermal management. Historically, junction temperature is calculated using ambient or case temperature, junction-to-ambient (ja) or junction to-case (jc) thermal resistance, and device power consumption.
Page 431 (mV) of difference, as seen at the external TSD pins. Switching the I/O near the TSD pins can affect the temperature reading. Altera recommends taking temperature readings during periods of inactivity in the device or use the internal TSD with built-in ADC circuitry.
Page 432 ■ Updated the “Temperature Sensing Diode” and “External Pin Connections” sections. ■ Updated Equation 13–1. ■ November 2009 Removed Table 13-2: Stratix IV External Power Supply Pins. ■ Minor text edits. ■ Updated the “External Pin Connections” section. ■ June 2009 Added an introductory paragraph to increase search ability.
Page 433: About This Handbook
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 434 Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Altera Stratix IV Handbook

Chapter Revision Dates

Section I. Device Core

Chapter 1. Overview for the Stratix IV Device Family

Chapter 2 .Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices

Chapter 3. Trimatrix Embedded Memory Blocks in Stratix IV Devices

Chapter 4. DSP Blocks in Stratix IV Devices

Chapter 5 .Clock Networks and Plls in Stratix IV Devices

Chapter 6 .I/O Features in Stratix IV Devices

Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices

Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices

Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

Chapter 11 .SEU Mitigation in Stratix IV Devices

Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices

Chapter 13 .Power Management in Stratix IV Devices

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Summary of Contents for Altera Stratix IV