Altera Stratix IV Device Handbook page 830

Chapter 4: Reset Control and Power Down in Stratix IV Devices
PMA Direct Drive Mode Reset Sequences
3. After the PLL_L/R locks, as indicated by the locked signal going high (marker 4),
the transmitter is ready to accept parallel data from the FPGA fabric and
subsequently transmitting serial data reliably.
Figure 4–15. Reset Sequence Timing Diagram of Four Transmitter-Only Channels in Basic (PMA Direct) Drive ×4
Functional Mode
Reset and Power-Down Signals
pll_powerdown
Output Status Signals
pll_locked
Locked (output of PLL_L/R)
Note to Figure 4–15:
(1) For t duration, refer to the
pll_powerdown
January 2014 Altera Corporation
t
pll_powerdown (1)
1 2
3
Keep the TX side user logic
under reset until this point
DC and Switching Characteristics for Stratix IV Devices
4
chapter.
4–27
Stratix IV Device Handbook
Volume 2: Transceivers