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Altera Stratix III Using Manual
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Altera Stratix III Using Manual

Altera Stratix III Using Manual

Using ddr3 sdram in devices
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© November 2008
Introduction
DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that
include lower power consumption, higher data bandwidth, enhanced signal quality with
multiple on-die termination (ODT) selection and output driver impedance control.
DDR3 SDRAM brings higher memory performance to a broad range of applications, such as
PCs, embedded processor systems, image processing, storage, communications, and
networking.
Although DDR2 SDRAM is currently the more popular SDRAM, to save system power and
increase system performance you should consider using DDR3 SDRAM. DDR3 SDRAM
offers lower power by using 1.5 V for the supply and I/O voltage compared to the 1.8-V
supply and I/O voltage used by DDR2 SDRAM. DDR3 SDRAM also has better maximum
throughput compared to DDR2 SDRAM by increasing the data rate per pin and the number
of banks (8 banks are standard).
1
The Altera
controller only support local interfaces running at half the rate of the memory
interface.
Altera Stratix
DQS, write-, and read-leveling circuitry.
Table 1
displays the maximum clock frequency for DDR3 SDRAM in Stratix III devices.
Table 1. DDR3 SDRAM Maximum Clock Frequency Supported in Stratix III Devices
Speed Grade
–2
–3 and I3
–4, 4L, and I4L at 1.1 V
–4, 4L, and I4L at 0.9 V
Notes to
Table
1:
(1) Numbers are preliminary until characterization is final. The supported operating frequencies are memory interface maximums for the device
family. Your design's actual achievable performance is based on design and system specific factors and static timing analysis of the completed
design.
(2) Applies to modules and components using fly-by termination with leveling scheme.
(3) Timing can close at the target speed in the Quartus II software version 8.0. In Quartus II software version 8.1, you can use these designs for
prototyping, but you should not go to production until Altera releases final DDR3 models in Quartus II software version 9.0..
(4) Performance is based on 1.1-V core voltage. At 1.1-V core voltage, the –4L speed grade devices have the same performance as the –4 speed
grade devices.
(5) The Quartus II software version 8.1 does not support DDR3 SDRAM below 360 MHz. The DLL mode is not supported below 360 MHz. The
Quartus II software incorrectly shows that the design meets I/O timing.
© November 2008 Altera Corporation
AN 436: Using DDR3 SDRAM in Stratix III
ALTMEMPHY megafunction and DDR3 SDRAM high-performance
®
III and Stratix IV devices support DDR3 SDRAM interfaces with dedicated
®
and Stratix IV Devices
(Note
1),
(2)
f
(MHz)
MAX
533
(3)
400
333 (4),
(5)
Not supported
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
AN-436-4.0

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Summary of Contents for Altera Stratix III

  • Page 1 (3) Timing can close at the target speed in the Quartus II software version 8.0. In Quartus II software version 8.1, you can use these designs for prototyping, but you should not go to production until Altera releases final DDR3 models in Quartus II software version 9.0..
  • Page 2 Device Handbook. This application note describes the FPGA design flow to implement external memory interfaces using Stratix III and Stratix IV devices, and provides design guidelines. DDR3 SDRAMs are available as components and modules, such as DIMMs, SODIMMs, and RDIMMs. This application note describes implementing DDR3...
  • Page 3 DDR3 SDRAM has a maximum frequency of 800 MHz or 1600 Mbps per DQ pin. DDR3 SDRAM minimum operating frequency is 300 MHz. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...

  • Page 4: Dqs Postamble Circuitry

    Note to Table (1) The Altera DDR and DDR2 SDRAM high-performance controllers do not support additive latency. IOE Dedicated DDR3 SDRAM Features Stratix III devices have enhanced upon the IOE DDR capabilities of previous generations of devices by including the following functionality availability directly in the IOE.
  • Page 5 ALTIOBUF megafunction—allows you to parameterize the device IO Device Pin Utilization Table 3 shows the DDR3 SDRAM interface pins and how to connect them to Stratix III pins. Table 3. Stratix III DDR3 SDRAM Interface Pin Utilization (Part 1 of 2)
  • Page 6 IP in the Quartus II software before PCB sign-off. Table 4 shows the number of DDR3 SDRAM suitable DQS and DQ groups available in Stratix III devices per side. Table 4. Number of DQS and DQ Groups in Stratix III Devices per Side Package Side ×4 ×8/×9...
  • Page 7 The memory controller delays the DQS signal during a read, so that the DQ and DQS signals are center aligned at the capture register. Stratix III devices use a phase-locked loop (PLL) to center-align the DQS signal with respect to the DQ signals during writes and use DLL-controlled DQS phase-shift circuitry to shift the incoming DQS signal during reads.
  • Page 8 (C) counters. This increased number of PLL outputs allows for the use of dedicated clock phases. In general, each Stratix III PLL has access to 4 global clocks (GCLK) and 6 regional clocks (RCLK) (left and right) or 10 RCLK (top and bottom).
  • Page 9 Background Page 9 Figure 1. PLL and DLL Locations and Resources in Stratix III Devices PLL_R1 PLL_L1 PLL_T1 PLL_T2 DLL4 DLL1 RCLK[87:82] RCLK[63:54] RCLK[53:45] RCLK[81:76] GCLK[15:12] PLL_R2 PLL_L2 RCLK[5:0] RCLK[43:38] GCLK[3:0] GCLK[11:8] PLL_L3 PLL_R3 RCLK[11:6] RCLK[37:32] GCLK[7:4] RCLK[69:64] RCLK[21:12] RCLK[31:22]...
  • Page 10 Figure 2 Figure 3 show the Stratix III IOE structure. Figure 2. Stratix III IOE Input Registers Notes: (1) You can bypass each register except the first in this path. (2) The 0-phase resynchronization clock from the read-leveling delay chain.
  • Page 11 Figure 3. Stratix III IOE Output Registers Half Data Rate to Single Data Rate Output-Enable Registers Alignment Registers (4) From Core (2) Double Data Rate Output-Enable Registers From Core (2) OE Reg A Half Data Rate to Single Data Rate Output Registers...
  • Page 12 DDR I/O structures can be directly implemented in the IOE, thus saving core logic and ensuring tight skew is easily maintained, which eases timing. Stratix III devices now feature four DLLs, so DQS capture mode is now supported on every side of the device.
  • Page 13 ALTMEMPHY-based designs do not use dynamic delay chains to deskew interfaces. Read and Write Leveling Stratix III I/O registers include read- and write-leveling circuitry to enable skew to be removed or applied to the interface on a DQS group basis. There is one leveling circuit located in each I/O subbank.
  • Page 14 All class I signals are multiload signals—they either go to a DIMM that has multiple memory devices, or they go to all memory devices that make up the interface. Altera recommends the ideal topology is a daisy-chained serial structure. Altera gives the following recommendations for the class I termination to V ■...
  • Page 15 ALTMEMPHY Megafunction Overview The Altera ALTMEMPHY megafunction allows the rapid creation of a physical layer interface (PHY) in Stratix III devices. The PHY safely transfers data between memory and user logic. The easy-to-use ALTMEMPHY megafunction GUI enables the rapid configuration of the highly configurable PHY. You can use the ALTMEMPHY megafunction with either a user-designed controller or the Altera DDR3 SDRAM high-performance controller.

  • Page 16: Select A Device

    Stratix III devices. These guidelines provide the fastest out-of-the-box experience with external memory interfaces in Stratix III devices. Each step is discussed in detail in the following sections. This flow uses the DDR3 SDRAM high-performance controller.
  • Page 17 “Address and Command, Clock, and Other Signals” Memory controllers in Stratix III devices require access to dedicated IOE features, PLLs, and several clock networks. Stratix III devices are feature rich in all of these areas, so you must consider detailed resource and pin planning whenever implementing complex IP or multiple IP cores.
  • Page 18 ■ Top or bottom PLLs in Stratix III devices connect to ten maximum regional clock nets Left or right PLLs in Stratix III devices connect to six maximum regional clock nets ■ ■ EP3S...80 and larger devices have two PLLs located in the middle of each side of the device ■...
  • Page 19 (downstream) PLL should have a high-bandwidth setting In Stratix III devices, two PLLs may be cascaded to each other through the clock ■ network. In addition, where two PLLs exist adjacent to each other, there is a direct connection between them that does not require the global clock network.
  • Page 20 DDR3 SDRAM interfaces in Stratix III devices use DQS phase-shift circuitry for data capture. All Stratix III devices include a total of four DLLs: one located in each corner of the device. Each DLL can support two different phase offsets, and each DLL can access the two sides adjacent to its location.
  • Page 21 DLL. More may be possible, depending on the phase shift required. Altera memory IP always specifies a default optimal phase setting, to override this setting, refer to the respective IP user guide.
  • Page 22 (5) Hybrid DDR3 SDRAM interfaces are not supported in –3 and –4 speed grade devices, because of the 300-MHz minimum frequency requirement. DQ and DQS Width Limits Stratix III devices do not limit the width of DDR3 SDRAM interfaces beyond the following requirements: The entire interface DQ, clock, and address signals should reside within the same ■...
  • Page 23 ■ The greater the number of banks, the greater the skew, hence Altera recommends that you always generate a test project of your desired configuration and confirm that it meets timing...
  • Page 24 ×36 groups, if they have pins they are using for RUP and RDN. The Quartus II software may not place these pins correctly and may give you a no-fit. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 25 II software that targets the device and memory type. ® When instantiating the datapath for DDR3 SDRAM interfaces in Stratix III devices, Altera recommends that you use the ALTMEMPHY megafunction for the datapath and PHY. The ALTMEMPHY megafunction features a license-free PHY that you may use with the Altera SDRAM high-performance controllers or your own custom controller.
  • Page 26 The advanced I/O timing option is turned on by default for Stratix III devices. Ensure that the overall board trace models are a reasonable approximation for each I/O standard on each PCB.
  • Page 27 PCB and the far transmission line to represent the DIMM. The board trace model should only include PCB or off chip information. Do not include the Stratix III I/O pin and package capacitance, OCT, or drive strength settings, as the Quartus II software ascertains these dynamically.
  • Page 28 Core reset and removal setup and hold margin ■ ■ Write setup and hold margin ■ Read capture setup and hold margin ■ Read resynchronization setup and hold margin AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 29 AN 520: DDR3 SDRAM Interface Termination and Layout Guidelines. Trace information from your board-level simulation should be fed back into the Quartus II advanced I/O timing information. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 30 FPGA side, which simplifies board design and reduces overall board cost. You can dynamically switch between the series and parallel OCT resistor depending on whether the Stratix III devices are performing a write or a read operation. The OCT features offer user-mode calibration to compensate for any variation in VT during normal operation to ensure that the OCT values remain constant.
  • Page 31 SDRAM interface. This example design also provides some recommended settings, including termination scheme and drive strength setting, to simplify the design. The example design targets the Stratix III Memory Demonstration Kit, which includes a DIMM module (MT9JSF12872AY-1G1BZES). This flow applies to any other development kit or PCB.
  • Page 32 To select the DDR3 SDRAM High Performance Controller in the Interfaces section of the MegaWizard Plug-In Manager, see Figure 8. For this example, enter ddr3_dimm for the name of the DDR3 SDRAM high-performance controller. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 33 DDR3 SDRAM interfaces on Stratix III devices). 4. For the memory preset, select S3MB1_Derated (Micron MT9JSF12872AY-1G1BZES), which gives a 72-bit wide 1,152-MB 533-MHz DDR3 unbuffered DIMM, see Figure © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 34 5. To create a memory preset click Modify parameters. In the Preset Editor dialog box, you can modify the memory presets, see Figure AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 35 RTD calculations and non-DQS capture mode. The wizard does not require these parameters, so use the default values. The t , and t parameters typically require slew rate derating. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 36 Simulation and measurement show the following slew rate for the clock, address and command, and DQ and DQS pins on the Stratix III Memory Demonstration Board when using the default I/O standard and drive options: Address and command = 1.5 V/ns...
  • Page 37 DQ, DQS, DQS#, or DM pins, as the board was designed to use OCT. 9. Enter 240 in Dedicated clock phase for the Address/Command Clock Settings. Timing analysis shows that 240° is optimal for the Stratix III memory demonstration board. The settings in Auto-Calibration Simulation Options are for RTL simulation only and are not applicable for gate-level simulation.

  • Page 38: Timing Analyzer

    <variation_name>_phy_assign_dq_groups.tcl, which relates the DQ and DQS pin groups together for the fitter to place them correctly in the Quartus II software. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 39 Start Analysis and Synthesis. 2. Assign all of your pins, so the Quartus II software fits your design correctly and gives correct timing analysis. To assign pin locations for the Stratix III memory demonstration board, run the Altera-provided S3_MB1_DDR3_PinLocations.tcl file or manually assign pin locations by using the Pin Planner.
  • Page 40 DQ group order and DQ pin order within each group is not important. However, you must place DQ pins in the same group as their respective strobe pin. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 41 For more information on how to use the Quartus II Pin Planner, refer to the Management chapter in volume 2 of the Quartus II Handbook. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 42 Otherwise the Quartus II software optimizes the driver away, and the example driver fails. To assign virtual pin assignments for the Stratix III memory demonstration board, run the Altera-provided s3_MB1_ddr3_exdriver_vpin.tcl file or manually assign virtual pin assignments using the Assignment Editor.
  • Page 43 Figure 17 show a typical board trace model for a CAC, mem_clk, DQ, and DQS pin on the Stratix III memory demonstration board including the data for the MT9JSF12872AY-1G1 memory module. Figure 14. Stratix III Memory Demonstration Board CAC Signal Board Trace Model ©...
  • Page 44 Page 44 Example Project Walkthrough Figure 15. Stratix III Memory Demonstration Board Memory Clock Signal Board Trace Model Figure 16. Stratix III Memory Demonstration Board DQ Signal Board Trace Model AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 45 Example Project Walkthrough Page 45 Figure 17. Stratix III Memory Demonstration Board DQS Signal Board Trace Model Table 7 shows the board trace model parameters for the Stratix III development board. Table 7. Stratix III Development Board Trace Model Summary...
  • Page 46 (3) mem_clk Cn value of 4.6 pF comprises 7 pF on memory demonstration board plus 2.2 pF on the DIMM, which is 9.2 pF differential or 4.6 pF Altera recommends you use the Board Trace Model assignment on all DDR3 SDRAM interface signals. To apply board trace model assignments for the Stratix III memory demonstration board, run the Altera-provided S3_MB1_DDR3_BTModels.tcl file or manually assign virtual pin assignments using the Quartus II Pin Planner.
  • Page 47 For example waveforms, refer to the DDR3 SDRAM High-Performance Controller User Guide. Compile Design and Verify Timing To compile the design, on the Processing menu, click Start Compilation. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 48 Create Timing Netlist and Read SDC. After a task is executed, it turns green. 3. After completing the tasks, run the report timing script by going to the Script menu and clicking Run Tcl Script. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 49 Report panel in TimeQuest timing analyzer and select the path that violates the hold time, as shown in Figure © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 50 After modifying the clk6 phase setting, recompile the design for the new PLL setting to take effect. Run the report timing script again. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 51 Determine Board Design Constraints and Perform Board-Level Simulations Stratix III devices support both series and parallel OCT resistors to improve signal integrity. Another benefit of the Stratix III OCT resistors is eliminating the need for external termination resistors on the FPGA side. This feature simplifies board design and reduces overall board cost.
  • Page 52 DDR3 SDRAM with the ODT feature turned on and using the 50-Ω series OCT feature of the Stratix III FPGA device. Figure 22. Write Operation Using Parallel ODT and 60-Ω Series OCT of the Stratix III FPGA Device DDR3 DIMM...
  • Page 53 For more information on using the SignalTap II logic analyzer, refer to the following documents: ■ Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 54 7. On the Edit menu, click Add Nodes. 8. Search for specific nodes by typing *local* in the Named box, for Filter select SignalTap II: pre-synthesis and click List. AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 55 ■ local_rdata ■ local_wdata ■ pnf_per_byte ctl_wlat ■ ctl_rlat ■ 12. Right-click Trigger Conditions for the test_complete signal and select Rising Edge. © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 56 The SOF Manager should contain the <your project name>.sof file. To add the correct file to the SOF Manager, follow these steps: AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation...
  • Page 57 Run Analysis to run once, or click Autorun Analysis to run continuously. Figure 27 shows the design analysis. Figure 27. SignalTap II Example DDR3 SDRAM Design Analysis © November 2008 Altera Corporation AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices...
  • Page 58 Page 58 Conclusion Conclusion Stratix III devices have dedicated circuitry to interface with DDR3 SDRAM at speeds up to 400 MHz (800 Mbps) with comfortable and consistent margins. The advanced clocking features available in Stratix III devices allow for a high-performance, versatile interface to DDR3 SDRAM.

  • Page 59: Document Revision History

    Copyright © November 2008. Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S.

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Stratix iv