Altera Stratix IV Device Handbook page 292

8–10
Table 8–7. Port List of the LVDS Interface (ALTLVDS)
Port Name
LVDS Receiver Interface Signals
rx_in
rx_inclock
rx_channel_data_align
rx_dpll_hold
(3)
rx_enable
rx_out[ ]
rx_outclock
rx_locked
rx dpa locked
rx_cda_max
rx_divfwdclk
dpa_pll_recal
Stratix IV Device Handbook
Volume 1
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
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, (Part 2 of 3)
Input /
Output
Input LVDS receiver serial data input port.
Reference clock input for the receiver PLL.
The ALTLVDS MegaWizard Plug-In Manager software automatically selects
the appropriate PLL multiplication factor based on the data rate and
Input reference clock frequency selection.
For more information about the allowed frequency range for this reference
clock, refer to the "High-Speed I/O Specification" section in the
Switching Characteristics for Stratix IV Devices
Edge-sensitive bit-slip control signal. Each rising edge on this signal causes
the data re-alignment circuitry to shift the word boundary by one bit. The
Input
minimum pulse width requirement is one parallel clock cycle. There is no
maximum pulse width requirement.
When low, the DPA tracks any dynamic phase variations between the clock
and data. When high, the DPA holds the last locked phase and does not
Input
track any dynamic phase variations between the clock and data. This port is
not available in non-DPA mode.
This port is instantiated only when you select the Use External PLL option
in the MegaWizard Plug-In Manager software. This input port must be
Input
driven by the PLL instantiated though the ALTPLL MegaWizard Plug-In
Manager software.
Receiver parallel data output. The data bus width per channel is the same as
the deserialization factor (DF). The output data is synchronous to the
Output
rx_outclock signal in non-DPA and DPA modes. It is synchronous to the
rx_divfwdclk signal in soft-CDR mode.
Parallel output clock from the receiver PLL. The parallel data output from
the receiver is synchronous to this clock in non-DPA and DPA modes. This
port is not available when you select the Use External PLL option in the
Output
MegaWizard Plug-In Manager software. The FPGA fabric-receiver interface
clock must be driven by the PLL instantiated through the ALTPLL
MegaWizard Plug-In Manager software.
When high, this signal indicates that the receiver PLL is locked to
Output
rx_inclock.
This signal only indicates an initial DPA lock condition to the optimum
phase after power up or reset. This signal is not de-asserted if the DPA
Output selects a new phase out of the eight clock phases to sample the received
data. You must not use the rx_dpa_locked signal to determine a DPA
loss-of-lock condition.
Data re-alignment (bit slip) roll-over signal. When high for one parallel clock
Output cycle, this signal indicates that the user-programmed number of bits for the
word boundary to roll-over have been slipped.
Parallel DPA clock to the FPGA fabric logic array. The parallel receiver
Output output data to the FPGA fabric logic array is synchronous to this clock in
soft-CDR mode. This signal is not available in non-DPA and DPA modes.
Enable PLL calibration dynamically without resetting the DPA circuitry or
Input
the PLL.
Description
chapter.
September 2012 Altera Corporation
ALTLVDS Port List
DC and