Guidelines To Debug Transceiver-Based Designs; Guidelines To Debug The Fpga Logic And The Transceiver Interface - Altera Stratix IV Device Handbook

2–14
Include all the libraries in the search path. Add the ALTGX and ALTGX_RECONFIG
MegaWizard Plug-In Manager-generated wrapper files (.v or .vhd) and all of the
design files to the library. Compile all the library files first, then the design files, and
lastly run the simulation.
For Verilog simulation, add the ALTGX and ALTGX_RECONFIG MegaWizard
Plug-In Manager-generated Verilog wrapper files (.v), the Altera library files, and all
of the design files. Compile all the library files first, then the simulation model file,
followed by the design files. Lastly, run the simulation.
These guidelines are further described in
Application"
f
For more information about functional register transfer level (RTL) simulation or
post-fit simulation, refer to the
Handbook.

Guidelines to Debug Transceiver-Based Designs

This section provides guidelines to debug transceiver-based designs. If a system
failure occurs, the first step is to ensure the functionality of the logic within the FPGA.
Use the following information when you observe a system failure.

Guidelines to Debug the FPGA Logic and the Transceiver Interface

Before checking the functionality in silicon, perform functional simulation to ensure
the basic functionality of the RTL and the transceiver-FPGA fabric interface.
■ Understand the limitations of functional simulation. If you intend to simulate
timing parameters, consider post-fit simulation. The functional simulation model
for transceivers does not model timing-related parameters or uncertainties in the
transceiver data path. For example, the PPM difference in the rate matcher clocks
(clock rate compensation) or the phase differences between the read and write side
of the phase compensation FIFO are not modeled.
f
Check whether the compiled design has timing violations in the TimeQuest
■
Timing Analyzer report. Set the appropriate timing constraints on the failing
paths.
f
■ Verify the functionality of the transmitter and receiver data path with serial
loopback. Dynamically control the serial loopback through the rx_seriallpbken
port. When this signal is asserted, data from the transmitter serializer is looped
back to the receiver CDR of the channel.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
below.
Simulation
For information about functional RTL simulation or post-fit simulation,
refer to the Simulation chapter in volume 3 of the Quartus II Handbook.
For information about using the TimeQuest Timing Analyzer, refer to the
The Quartus II TimeQuest Timing Analyzer
Quartus II Handbook.
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Guidelines to Debug Transceiver-Based Designs
"Example 1: Fibre Channel Protocol
chapter in volume 3 of the Quartus II
chapter in volume 3 of the
February 2011 Altera Corporation