Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–14. Two-Multiplier Adder Mode Shown for a Half DSP Block
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
Note to
(1) Block output for accumulator overflow and saturate overflow.
February 2011 Altera Corporation
clock[3..0]
ena[3..0]
aclr[3..0]
Half-DSP Block
Figure
4–14:
signa
signb
output_round
output_saturate
+
4–23
overflow (1)
result[ ]
Stratix IV Device Handbook
Volume 1
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