Clock And Reset; Test Pins; Emif (External Memory Interface) - Siemens ERTEC200 Manual

1.5.4

Clock and Reset

No. Signal Name
42 CLKP_A
43 CLKP_B
44 F_CLK
45 REF_CLK
46 RESET_N
1.5.5

Test Pins

No. Signal Name
47 TEST_N (3)
48 TMC1 (3)
49 TMC2 (3)
50 TACT_N (3)
1.5.6

EMIF (External Memory Interface)

No. Signal Name
51 DTR_N
52 OE_DRIVER_N
53 A0
54 A1
55 A2
56 A3
57 A4
58 A5
59 A6
60 A7
61 A8
62 A9
63 A10
64 A11
65 A12
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
I/O Pull- PIN
(Reset) No.
CLOCK / RESET GENERATION
I (I) B14
O D14
I (I) B13
Dependent A15
on PIN
CONFIG[1]
I (I) up B7
I/O Pull- PIN
(Reset) No.
TEST
I (I) up T5
I (I) G5
I (I) H6
I (I) dn J5
Alternative I/O
Reset Function (Reset)
EMIF (External Memory Interface)
BOOT0 B (I)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
Comment
Quartz connection
Quartz connection
F_CLK for F-counter
Tristate or
reference clock output, 25 MHz
PowerOn reset
Comment
Test mode
Test configuration
Test configuration
TESTACT-TAP reset
Pull- PIN Comment
No.
up E7 Direction signal for external driver
or scan clock (Scan mode)
ERTEC 200 boot mode (external
PD may be necessary)
D8 Enable signal for external driver
or scan clock (Scan mode)
B4 Address bit 0
SDRAM: Bank address 0
A3 Address bit 1
SDRAM: Bank address 1
B3 Address bit 2
SDRAM: Address 0
B2 Address bit 3
SDRAM: Address 1
D4 Address bit 4
SDRAM: Address 2
C2 Address bit 5
SDRAM: Address 3
C1 Address bit 6
SDRAM: Address 4
D2 Address bit 7
SDRAM: Address 5
D1 Address bit 8
SDRAM: Address 6
E2 Address bit 9
SDRAM: Address 7
E1 Address bit 10
SDRAM: Address 8
F2 Address bit 11
SDRAM: Address 9
F1 Address bit 12
SDRAM: Address 10
14
ERTEC 200 Manual
Version 1.1.0