Siemens ERTEC200 Manual page 73

Extended Config
Description Setting of additional functionalities
Bit No. Name
31 Reserved
30 TEST_1
29 TEST_2
28..26 Reserved
25 ADB
24 ASDB
23..20 Reserved
19 TEST_3
18 Reserved
17..16 BURST_LENGTH
15 Reserved
14 TRCD/TCD
13..9 Reserved
8 SDSIZE
7 ATIRQ
6..0 Reserved
Programming specification for EMIR registers:
For a correct setting of the SDRAM, the values for Burst_Length and SDRAM bank width must match up in the Extended
Config register. The bits must be set before the MODE-Register-SET command is initiated; otherwise, they are not
transferred to the SDRAM. The Mode-Register-Set command is initiated by writing to the bits [15:8] of the SDRAM-
Bank-Config register when bit 29 = 1 in the SDRAM Refresh Control register.
SDRAM 32-bit data width: Extended Config[8] = 0
Extended Config[17:16] = 11 Full Page, Read INCR_S Burst Length = 8
Extended Config[17:16] = 10 Full Page, Read INCR_S Burst Length = 4
Extended Config[17:16] = 00 Burst Length = 1
SDRAM 16-bit data width: Extended Config[8] = 1
Extended Config[17:16] = 11 Full Page, Read INCR_S Burst Length = 8
Extended Config[17:16] = 10 Full Page, Read INCR_S Burst Length = 4
Extended Config[17:16] = 01 Burst Length = 2
All other settings cause malfunctions
The Mode Register Set command is initiated by writing to the bit in the register SDRAM_Bank_Config[15:8]. (Register
SDRAM_Refresh-Control[29] =1)
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
W/R Addr.: 0x7000_0020
Description
Reserved
Test Mode 1
0: 200 µs delay after system reset (SDRAM power-up)
1: Delay after system reset is immediately terminated
Test Mode 2
0: Normal function
1: All SDRAM accesses are misses
Reserved
Active data bus
After each access to the SDRAM, the data bus is driven actively to 1 in order
to support integrated pull-ups.
Asynchronous active data bus
After each access to the asynchronous area, the data bus is driven actively
to 1 at the end of the Hold phase in order to support integrated pull-ups.
Reserved
Test Mode 3
0: Normal function
1: DTR_N = Test Output
Reserved
SDRAM burst length
00: 1
01: 2
10: Full Page, Read INCR_S burst length = 4
11: Full Page, Read INCR_S burst length = 8
Reserved
Time between the SDRAM commands
Activate and read/write, precharge and activate
0: 1 AHB clock cycles
1: 2 AHB clock cycle
Reserved
SDRAM bank size
0: 32-bit data bus
1: 16-bit data bus
0: Timeout watchdog for asynchronous accesses disabled
1: Timeout watchdog for asynchronous accesses enabled
After the watchdog expires (256 AHB clock cycles), an interrupt is triggered.
Setting Bit 7 to 0 deletes interrupt source.
Reserved
73
Default: 0x0303_0000
ERTEC 200 Manual
Version 1.1.0