4.4.2
4.5 Watchdog Timers ................................................................................................................................... 45
4.5.1
Watchdog Timer 0.......................................................................................................................... 45
4.5.2
Watchdog Timer 1.......................................................................................................................... 45
4.5.3
Watchdog Interrupt ........................................................................................................................ 45
4.5.4
WDOUT0_N................................................................................................................................... 45
4.5.5
WDOUT1_N................................................................................................................................... 45
4.5.6
Watchdog Registers....................................................................................................................... 46
4.5.7
4.5.8
4.6 UART Interface....................................................................................................................................... 48
4.6.1
4.6.2
UART Register Description............................................................................................................ 50
4.7 Synchronous Interface SPI..................................................................................................................... 54
4.7.1
4.7.2
SPI Register Description................................................................................................................ 56
4.8 System control register........................................................................................................................... 58
4.8.1
4.8.2
5
5.1.1
Clock Supply in ERTEC 200 .......................................................................................................... 64
5.1.2
JTAG Clock Supply........................................................................................................................ 65
5.1.3
5.2.1
PowerOn reset ............................................................................................................................... 65
5.2.2
Hardware Reset ............................................................................................................................. 66
5.2.3
Watchdog Reset ............................................................................................................................ 66
5.2.4
Software reset................................................................................................................................ 66
5.2.5
IRT Switch Reset ........................................................................................................................... 66
5.3.1
AHB Bus Monitoring....................................................................................................................... 67
5.3.2
APB Bus Monitoring....................................................................................................................... 67
5.3.3
EMIF Monitoring ............................................................................................................................ 67
6
6.2 EMIF Register Description ..................................................................................................................... 70
7
Local Bus Unit (LBU). ............................................................................................................74
7.1 Page Range Setting ............................................................................................................................... 76
7.2 Page Offset Setting ................................................................................................................................ 76
7.3 LBU Address Mapping ........................................................................................................................... 77
7.4 Page Control Setting .............................................................................................................................. 78
7.5.1
7.5.2
7.5.3
7.5.4
7.6 Host Interrupt Handling: ......................................................................................................................... 82
7.8 LBU Register Description ....................................................................................................................... 83
8
DMA-Controller.......................................................................................................................85
9
Multiport Ethernet PHY..........................................................................................................88
10
Memory Description...............................................................................................................91
11
Test and Debugging...............................................................................................................94
11.1.1 Trace Modes.................................................................................................................................. 94
Page 6
ERTEC 200 Manual