Contents
1
Introduction ............................................................................................................................9
1.2 Features of the ERTEC 200 ................................................................................................................... 9
1.4 ERTEC 200 Package ............................................................................................................................. 11
1.5.1
1.5.2
JTAG and Debug ........................................................................................................................... 13
1.5.3
Trace Port ...................................................................................................................................... 13
1.5.4
Clock and Reset ............................................................................................................................ 14
1.5.5
Test Pins........................................................................................................................................ 14
1.5.6
1.5.7
1.5.8
Ethernet PHY1 and PHY2.............................................................................................................. 18
1.5.9
Power Supply................................................................................................................................. 19
2
ARM946E-S Processor ..........................................................................................................21
2.1 Structure of ARM946E-S........................................................................................................................ 21
2.2 Description of ARM946E-S .................................................................................................................... 22
2.9.1
Prioritization of Interrupts ............................................................................................................... 24
2.9.2
Trigger Modes................................................................................................................................ 24
2.9.3
2.9.4
Software Interrupts for IRQ ............................................................................................................ 24
2.9.5
Nested Interrupt Structure.............................................................................................................. 24
2.9.6
EOI End-Of-Interrupt...................................................................................................................... 24
2.9.7
IRQ Interrupt Sources .................................................................................................................... 25
2.9.8
FIQ Interrupt Sources .................................................................................................................... 25
2.9.9
2.10 ARM946E-S Register ............................................................................................................................. 31
3
3.1.1
AHB Arbiter.................................................................................................................................... 32
3.1.2
AHB Master-Slave Coupling .......................................................................................................... 32
3.2 APB I/O Bus ........................................................................................................................................... 32
4
I/O on APB bus .......................................................................................................................33
4.1 BOOT ROM............................................................................................................................................ 33
4.1.1
Booting from External ROM ........................................................................................................... 34
4.1.2
Booting via SPI .............................................................................................................................. 34
4.1.3
Booting via UART .......................................................................................................................... 34
4.1.4
Booting via LBU ............................................................................................................................. 34
4.1.5
Memory Swapping ......................................................................................................................... 34
4.2.1
4.2.2
GPIO Register Description............................................................................................................. 36
4.3 Timer 0/1/2 ............................................................................................................................................. 38
4.3.1
Timer 0 and Timer 1....................................................................................................................... 38
4.3.1.1
Timer 0/1 Interrupts............................................................................................................... 39
4.3.1.2
Timer 0/1 Prescaler............................................................................................................... 39
4.3.1.3
Cascading of Timers 0/1 ....................................................................................................... 39
4.3.2
Timer 2........................................................................................................................................... 39
4.3.3
4.3.4
Timer Register Description ............................................................................................................ 40
4.4 F-Timer Function .................................................................................................................................... 43
4.4.1
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
Page 5
ERTEC 200 Manual
Version 1.1.0