Irq Interrupts As Fiq Interrupt Sources; 2.9.10 Interrupt Control Register - Siemens ERTEC200 Manual

2.9.9

IRQ Interrupts as FIQ Interrupt Sources

Interrupts from the IRQ interrupt can be placed on FIQ6 and FIQ7 können.
The interrupts of the FIQ interrupt controller are used for debugging, monitoring address area access, and for the
watchdog.
FIQ interrupts no. 4 and 5 are the interrupts for embedded ICE RT communication. The UART can also be used as a
debugger in place of the ICE. Effective real-time debugging is possible when the IRQ interrupt sources of the UART are
mapped to the FIQs with the number 6 or 7. This enables debugging of interrupt routines.

2.9.10 Interrupt Control Register

The interrupt control registers are used to specify all aspects of control, prioritization, and masking of the IRQ/FIQ
interrupt controllers.
Offset Address
Register Name
IRVEC
FIVEC
LOCKREG
FIQ1SREG
FIQ2SREG
IRQACK
FIQACK
IRCLVEC
MASKALL
IRQEND
FIQEND
FIQPR0
FIQPR1
FIQPR2
FIQPR3
FIQPR4
FIQPR5
FIQPR6
FIQPR7
FIQISR
FIQIRR
FIQ_MASKREG
IRREG
MASKREG
ISREG
TRIGREG
EDGEREG
SWIRREG
PRIOREG 0
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
ICU
(Base Address 0x5000_0000)
Address Area
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
0x0010 4 bytes
0x0014 4 bytes
0x0018 4 bytes
0x001C 4 bytes
0x0020 4 bytes
0x0024 4 bytes
0x0028 4 bytes
0x002C 4 bytes
0x0030 4 bytes
0x0034 4 bytes
0x0038 4 bytes
0x003C 4 bytes
0x0040 4 bytes
0x0044 4 bytes
0x0048 4 bytes
0x004C 4 bytes
0x0050 4 bytes
0x0054 4 bytes
0x0058 4 bytes
0x005C 4 bytes
0x0060 4 bytes
0x0064 4 bytes
0x0068 4 bytes
0x006C 4 bytes
0x0070 4 bytes
Access Default
R 0xFFFFFFFF
R 0xFFFFFFFF
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R 0xFFFFFFFF
R 0xFFFFFFFF
W 0x----
R/W 0x00000001
W 0x----
W 0x----
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R/W 0x00000007
R 0x00000000
R 0x00000020
R/W 0x000000FF
R 0x000001xx
R/W 0x0000FFFF
R 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x0000000F
26
Description
Interrupt vector register
Fast interrupt vector register
Priority lock register
Fast int. request 1 select register
(FIQ6 on FIQ interrupt controller)
Fast int. request 2 select register
(FIQ7 on FIQ interrupt controller)
Interrupt vector register with IRQ
acknowledge
Fast interrupt vector register with
FIQ acknowledge
Interrupt request clear vector
Mask for all interrupts
End of IRQ interrupt
End of FIQ interrupt
FIQ priority register on input FIQ0
of the FIQ interrupt controller
FIQ priority register on input FIQ1
of the FIQ interrupt controller
FIQ priority register on input FIQ2
of the FIQ interrupt controller
FIQ priority register on input FIQ3
of the FIQ interrupt controller
FIQ priority register on input FIQ4
of the FIQ interrupt controller
FIQ priority register on input FIQ5
of the FIQ interrupt controller
FIQ priority register on input FIQ6
of the FIQ interrupt controller
FIQ priority register on input FIQ7
of the FIQ interrupt controller
FIQ in-service register
FIQ request register
FIQ interrupt mask register
Interrupt request register
Interrupt mask register
In-service register
Trigger select register
Edge select register
Software interrupt register
Priority register 0
ERTEC 200 Manual
Version 1.1.0