Lbu Read From Ertec 200 With Common Read/Write Line (Lbu_Rdy_N Active Low); Figure 15: Lbu-Read-Sequence With Common Rd/Wr Line; Table 27: Lbu Read Access Timing With Common Read/Write Line - Siemens ERTEC200 Manual

7.5.3

LBU Read from ERTEC 200 with common Read/Write line (LBU_RDY_N active low)

LBU_CS_R_N/
LBU_CS_M_N
LBU_WR
LBU_A(20:0)/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
LBU_RDY
LBU_D(15:0)

Figure 15: LBU-Read-Sequence with common RD/WR line

Parameter
t write signal deasserted to chip select asserted setup time
WCS
t address valid to chip select asserted setup time
ACS
t chip select asserted to ready enabled delay
CRE
t chip select asserted to data enable delay
CDE
t ready active pulse width
RAP
t ready asserted to data valid delay
RTD
t write signal inactive to chip select deasserted hold time
CWH
t address valid to chip select deasserted hold time
RAH
t data valid/enabled to chip select deasserted hold time
RDH
t read recovery time
RR

Table 27: LBU Read access timing with common Read/Write line

Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
t
WCS
t
ACS
t
CRE
t
CDE
Description
t
RAP
t
RTD
81
t
RR
t
CWH
t
CAH
t
CDH
Min Max
2 ns
0 ns
5 ns 12 ns
5 ns 12 ns
17 ns 23 ns
5 ns
0 ns
0 ns
0 ns 12 ns
25 ns
ERTEC 200 Manual
Version 1.1.0