Dma Register Address Assignment; Description Of Dma Registers; Table 32: Overview Of Dma Registers - Siemens ERTEC200 Manual

8.1

DMA Register Address Assignment

The DMA registers are 32 bits in width. The registers can be written to with 32-bit accesses only. Only the ARM946E-S
processor can access the registers.
Register Name
DMAC0_SRC_ADDR_REG
DMAC0_DEST_ADDR_REG
DMAC0_CONTR_REG
DMAC0_CONF_REG

Table 32: Overview of DMA Registers

8.2

Description of DMA Registers

(DMAC0SrcAddrReg)
DMA-Source Address
Description Start address of the data block to be transferred by the DMA controller
Bit No. Name
31..0 START_ADDRESS
(DMAC0DestAddrReg)
DMA-Destination Address
Description Target address oft he data block to be transferred by the DMA controller
Bit No. Name
31..0 DESTINATION_ADD
RESS
(DMAC0ContrReg)
Channel Control (*)
Description To define the data block length.
31..24 Reserved
23..21 D_DELAY_EXTENTI
ON
20..16 S_DELAY_EXTENTI
ON
15..0 BYTE_COUNT
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
DMA-Register
Offset Address
Address Area
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
W/R Addr.: 0x8000_0000
Description
Start address
Only word addresses are permitted; bits 0 and 1 are ignored
W/R Addr.: 0x8000_0004
Description
Target address
Only word addresses are permitted; bits 0 and 1 are ignored
W/R Addr.: 0x8000_0008
Extends the D_Delay in number of 50 MHz clocks (see Channel Config)
Extends the S_Delay in number of 50 MHz clocks (see Channel Config)
Number of bytes to be transferred. The byte count must be aligned with the
set bus width; that is, if a 32-bit byte count is set for the target or source, only
one 4-byte aligned byte count can be used.
(Start 0x8000_0000)
Access Default
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
Default: 0x0000_0000
Default: 0x0000_0000
Default: 0x0000_0000
86
Description
DMA Start address register
DMA target address register
DMA control register
DMA configuration register
ERTEC 200 Manual
Version 1.1.0