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Power-State is approximately 15 mW per PHY. The Low-Power-Mode is exited again with Link-Pulses or
Packets on the MII interface. The digital modes are reinitialized, but the configuration is not saved again. When
the Power Down state is exited, a 256-µs reset is generated internally to stabilize the PLL before the PHY is
again ready for operation.
Both PHYs generate one interrupt each, which are placed on interrupt input IRQ9 of the ARM946E-S interrupt controller.
The following event trigger the interrupt:
•
INT1:
Auto-Negotiation Page Received
•
INT2:
Parallel Detection Fault
•
INT3:
Auto-Negotiation LP-Acknowledge
•
INT4:
Link Down
•
INT5:
Remote Fault Detected
•
INT6:
Auto-Negotiation complete
•
INT7:
ENERGY On generated
•
INT8:
SMII elastic buffer overflow/underflow
The external circuitry of the UTP interface and the 100BASE-FX is presented in the description /xx/.
If the internal PHYs are not used, and external PHYs are connected to the MII interface instead, then all supply voltages
must still be routed to the internal PHYs and the reference voltage placed on the EXTRES pin. All other inputs of the
TX/FX interface must be connected to GND or VDD.
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
90
ERTEC 200 Manual
Version 1.1.0
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