Structure Of The Ertec 200; Figure 1: Ertec 200 Block Diagram - Siemens ERTEC200 Manual

1.3

Structure of the ERTEC 200

The figure below shows the function groups with the common communication paths.
External
LBU / MII + SMI /
Memory Interface
ETM / GPIO
48
MUX
74
48
Local
Controller
Memory-
Bus Unit
Controller
16 Bit
(EMIF)
(LBU)
Master Slave Master
Input
MUX/Arb.
stage
Multi-Layer-AHB
50 MHz/32Bit
3
16
16

Figure 1: ERTEC 200 Block Diagram

Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
ARM-
DMA-
Interrupt-
Controller
Slave Slave
14
Input
Decode Decode
stage
Input
stage
Master
AHB-
Wrapper
Slave
32 Bit
MC-Bus
Switch Control
Ethernet- Ethernet-
SMI
Port1 Port2
MII-1
MII-0
PHY PHY
(Port 1)
(Port 2)
JTAG / Debug
7
ARM946ES
BS-
with
TAP
I-Cache ,
(8kByte)
D-Cache ,
(4kByte)
ETM
D-TCM
Interface
(4kByte)
Master
13
Input
stage
MUX/Arb.
Slave
AHB-
Wrapper
Master
(50MHz) SC-Bus (50MHz)
2-Port Switch
Page 10
25MHz
TRACE_
REF_
F_CLK
CLK
CLK
1 1
1 1
Clock-Unit
1
APB
50MHz / 32 Bit
GPIO
AHB/APB
Bridge
1 x UART
SPI1
Interface
32 Bit
3 x Timer,
Watchdog,
F-Timer
K-SRAM
64 kByte
System
Control
Boot-
ROM
(8 kByte)
7
MC-PLL Signals
21
20
ERTEC 200 Manual
Version 1.1.0
1 Reset
PLL
4
Test
13
32
P
P
5
GPIO,
UART,
32
SPI,
o
Timer,
Watchdog,
8
r
t
2
s
PHY2
PHY1
ERTEC200