Lattice Semiconductor LatticeECP2M PCI Express x4 User Manual page 12

Lattice Semiconductor
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13) (Continued)
SMA
Designation
J44 LVDS_OUTN1
J46 LVDS_OUTP2
J48 LVDS_OUTN2
J50 LVDS_OUTP3
J52 LVDS_OUTN3
Test Pad Array
A 5 x 12 array of test pads are provided for the user to utilize for test points. This array provides 48 general I/O con-
tacts and 12 ground points.
Table 9. Test Pad Array BGA Reference
AA20 V17 W20
AA13 AE9 AF9
GND GND GND
K7 J6 K5
G7 G8 E6
High Speed Test Point
(see Appendix A, Figure 13)
DP1
General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
(see Appendix A, Figure 14)
U18
The LatticeECP2M Evaluation Board is equipped to an 84-ball BGA DDR2 SDRAM memory device such as a
Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation
board includes termination of address and command signals. It includes all power and external components
needed to demonstrate the memory controller of the LatticeECP2M device
LFE2M35E
Name Signal
PR53B
PR55A
PR55B
PR59A
PR59A
Test Points Array on Component Side
1 2 3 4
13 14 15 16
25 26 27 28
37 38 39 40
49 50 51 52
AC25 AC23
AB6 E23
GND GND
L5 P5
D5 G12
672-BGA
V25
W26
W25
Y26
AA26
5 6 7 8 9 10
17 18 19 20 21 22 23
29 30 31 32 33 34 35
41 42 43 44 45 46 47
53 54 55 56 57 58 59
AD26 AB21 AC22
E24 P26 P25
GND GND GND
N6 P4 R3
C8 E13 H17
12
LatticeECP2M PCI Express x4
Evaluation Board User's Guide
Termination
Description
100-ohm Differential
100-ohm Differential
11 12
24
36
48
60
AD12 AF12
U21 U19
GND GND
W5 Y4
E14 G17
Termination
Resistor(s)
R135
R137
W14 AB13
V21 J2
GND GND
U8 W6
D17 E17