Lattice Semiconductor LatticeECP2M PCI Express x4 User Manual page 2

Table of Contents

LatticeECP2M PCI Express x4

Lattice Semiconductor

Evaluation Board User's Guide

Introduction

This user's guide describes the LatticeECP2M PCI Express x4 Evaluation Board featuring the LatticeECP2M

FPGA device. The evaluation board has been designed to support the LatticeECP2M35 device and the

LatticeECP2M50 device. Different versions of the evaluation board are available that contain either the

LatticeECP2M35 device or the LatticeECP2M50 device. The stand-alone evaluation PCB provides a functional

platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to PCI

Express protocols.

The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test

and measurement equipment. Please note that boards populated with the LatticeECP2M-35 device have all avail-

able SERDES channels routed to the PCI Express, and in this case the SMAs are not active. The SMAs are avail-

able in larger density LatticeECP2M FPGAs ﬁtting the same footprint, but with additional SERDES channels. The

board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for

single-ended traces and 100-ohm for differential traces.

The board has several debugging and analyzing features for complete user evaluation of the LatticeECP2M device.

This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the

LatticeECP2M FPGA.

Figure 1. LatticeECP2M PCI Express x4 Evaluation Board

Table of Contents