Lattice Semiconductor LatticeECP2M PCI Express x4 User Manual page 11

Lattice Semiconductor
Note: LEDs will illuminate if connected to an unprogrammed FPGA pin. It is recommended that a pull-down be pro-
grammed on FPGA output pins.
17-Segment LED Display
(see Appendix A, Figure 14)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.
Figure 4. 17-Segment LED Display
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the
evaluation of several types of FPGA I/O buffers. The use of several termination schemes permits an easy interface
for each buffer type.
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13)
SMA
Designation
J37
J39
J45
J47
J49*
J51*
J38 LVDS_OUTP0
J40 LVDS_OUTN0
J42 LVDS_OUTP1
Segment BGA
A H2
B J3
C G1
D H3
E J7
F H5
G G5
H G6
K F3
M J8
N E1
P J9
R E3
S F5
T D3
U F6
DP C2
LFE2M35E
Name Signal
LVDS_INP0 PR37A
LVDS_INN0 PR37B
LVDS_INP1 PR41A
LVDS_INN1 PR41B
LVDS_INP2 PR51A
LVDS_INN2 PR51B
LVDS_INP3 PR57A
LVDS_INN3 PR57B
PR50A
PR50B
PR53A
LatticeECP2M PCI Express x4
Evaluation Board User's Guide
A
H
K M N
U
P
G
T S
R
F E
Termination
672-BGA Description
N23 100-ohm Differential
M21
P24 100-ohm Differential
P23
T24 100-ohm Differential
U24
V24 100-ohm Differential
W24
T23 100-ohm Differential
T22
V26 100-ohm Differential
11
B
C
D
DP
Termination
Resistor(s)
R130
R132
R134
R136
R131
R133