Table 10: Timing Display - Tektronix WFM5200 Technical Reference

Specifications

Table 10: Timing display

Characteristic
Input Timing Relative to External
Reference
Timing Display Zero Definition
Operation with input and reference
being different formats
Link B to Link A
Input Timing Reference to Other
Input
6
Performance requirement
WFM5200 Waveform Monitor Specifications and Performance Verification
Reference information
Display of Vertical and Horizontal timing
offset graphically and numerically. One clock
cycle resolution.
Patented proprietary display. Display Timing
difference between input and Ref at rear
panel or relative to an offset saved by the
user.
For vertical timing, conforms to SMPTE
RP168-2002.
For horizontal timing, zero delay analog
signals have coincident syncs. For digital
signals, timing is such that if converted to
analog by a WFM601A, then the resultant
analog signal is conincident with the
reference.
Timing zero is equivalent to nominal zero
delay on TG700. Also agrees with signal that
shows minimal shift on the waveform display
when going from internal to external.
Vertical timing, according to SMPTE RP168,
specifies that the lines with the start of the
broad pulses are aligned.
Compatible with any combination of frame
abd field rates. (See Table 32.) (See
Table 33.) (See Table 34.) In cases where
there are multiple ways to interpret the phase
relationship, multiple indicators of the phase
will be shown. The numeric display will
follow the smallest phase offset.
Display of dual link timing skew. Uncertainty
of ± 1.5 clocks or 20 ns.
For Simultaneous inputs, allows selection of
other channel as reference.