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S5-95F
Stored On-Delay and Reset
Example:
Output Q 1.0 is set 5 s after I 0.0.
Further changes in the signal state at input I 0.0 do not affect the output.
Input I 0.1 resets timer T 4 to its initial value and sets output Q 1.0 to zero.
Timing Diagram
Signal states
1
0
1
0
1
0
5
STL
A
I
0.0
L
KT 500.0
SS
T
4
A
I
0.1
R
T
4
NOP 0
NOP 0
A
T
4
=
Q
1.0
EWA 4NEB 812 6210-02
5
CSF
T 4
T
s
I 0.0
KT 500.0
TV
BI
DE
I 0.1
R
Q
I 0.0
I 0.1
Q 1.0
T 4
Time in s
H 1: Auxiliary relay
I 0.0
KT 500.0
I 0.1
Q 1.0
STEP 5 Operations
Circuit Diagram
I 0.1
H 1
I 0.0
Q 1.0
H 1
LAD
T 4
T
s
TV
BI
DE
R
Q
Q 1.0
H 1
8-23
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