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Testing the User Program and Storing It on the Memory Submodule
ISTACK Output on the PG 710/730/750 and 770 Programmers
Table 14-2 shows a programmer listing of ISTACK control bits. The control bits needed for fault
analysis are emphasized in bold type.
The righthand portion of the table shows the allocation of control bits to system data and absolute
addresses in the PLCs.
CONTROL BITS
NB
PBSSCH
BSTSCH
NB
NB
NB
STOZUS
STOANZ
NEUSTA
NB
UAFEHL
MAFEHL
ASPNEP
ASPNRA
KOPFNI
KEINAS
SYNFEH
NINEU
Table 14-3 shows the programmer ISTACK listing for the causes of errors. Causes of error required
for S5-95F fault analysis are emphasized in bold type.
INTERRUPT STACK
DEPTH:
01
BEF-REG:
0000
BST-STP:
5E03
ACCU1:
FFFF
CONDITION CODE BITS:
CAUSE OF FAULT:
14-6
Table 14-2. Control Bits
SCHTAE
ADRBAU
SPABBR
REMAN
NB
NB
NB
BATPUF
NB
X
EOVH
NB
AF
PROEND
ASPNEEP
PADRFE
NB
NB
NB
Table 14-3. Interrupt Stack
SAC:
25CA
OB-NO.:
1
REL-SAC:
0000
ACCU2:
0000
CC1
CC0
STATUS
RLO
X
STOPS
NB
X
STUEB
NAU
ASPFA
NAUAS
QUITT
NB
NB
BARB
BARBEND
NB
NB
ASPLUE
RAMADFE
SUMF
URLAD
DB-ADR:
0000
DB-NO.:
OVFL
CARRY
SUF
TRAF
QVZ
ZYK
S5-95F
System
Absolute
data
S5-95F
word (SD)
address
SD 5
5D0A H
SD 6
5D0C H
SD 7
5D0E H
OR
ERAB
X
NNN
STS
PEU
BAU
EWA 4NEB 812 6210-02
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